Re: [Qemu-devel] [PATCH v3 04/13] target/mips: Add emulation of MMI instruction PEXCH

[Aleksandar Markovic]

> From: Mateja Marjanovic <address@hidden>
> Subject: [PATCH v3 04/13] target/mips: Add emulation of MMI instruction PEXCH
>
> From: Mateja Marjanovic <address@hidden>
>
> Add emulation of MMI instruction PEXCH. The emulation is implemented
> using TCG front end operations directly to achieve better performance.
>
> Signed-off-by: Mateja Marjanovic <address@hidden>
> ---
>  target/mips/translate.c | 97 
> ++++++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 96 insertions(+), 1 deletion(-)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 4763e06..9472477 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -24488,6 +24488,99 @@ static void gen_mmi_pcpyud(DisasContext *ctx)
>      }
>  }
>
> +/*
> + *  PEXCH rd, rt
> + *
> + *  Parallel Exchange Center Halfword

The text in the last line should be indented for consistency with previuos\
patches:

 *    Parallel Exchange Center Halfword

> + *
> + *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> + *  +-----------+---------+---------+---------+---------+-----------+
> + *  |    MMI    |0 0 0 0 0|   rt    |   rd    |  PEXCH  |    MMI3   |
> + *  +-----------+---------+---------+---------+---------+-----------+
> + */
> +static void gen_mmi_pexch(DisasContext *ctx)
> +{
> +    uint32_t pd, rt, rd;
> +    uint32_t opcode;
> +
> +    opcode = ctx->opcode;
> +
> +    pd = extract32(opcode, 21, 5);
> +    rt = extract32(opcode, 16, 5);
> +    rd = extract32(opcode, 11, 5);
> +
> +    if (unlikely(pd != 0)) {
> +        generate_exception_end(ctx, EXCP_RI);
> +    } else if (rd == 0) {
> +        /* nop */
> +    } else if (rt == 0) {
> +        tcg_gen_movi_i64(cpu_gpr[rd], 0);
> +        tcg_gen_movi_i64(cpu_mmr[rd], 0);
> +    } else if (rd == rt) {
> +        TCGv_i64 t0 = tcg_temp_new();
> +        TCGv_i64 t1 = tcg_temp_new();
> +        uint64_t mask0 = (1ULL << 16) - 1;
> +        uint64_t mask1 = mask0 << 16;
> +        uint64_t mask2 = mask1 << 16;

The last line is clearer this way, IMHO:

        uint64_t mask2 = mask0 << 32;

> +        uint64_t mask3 = (mask2 << 16) | mask0;

...and this line this way:

        uint64_t mask3 = (mask0 << 48) | mask0;

> +
> +        tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
> +        tcg_gen_shli_i64(t0, t0, 16);
> +        tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2);
> +        tcg_gen_shri_i64(t1, t1, 16);
> +
> +        tcg_gen_andi_i64(cpu_gpr[rd], cpu_gpr[rd], mask3);
> +        tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t0);
> +        tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t1);
> +
> +        tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1);
> +        tcg_gen_shli_i64(t0, t0, 16);
> +        tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2);
> +        tcg_gen_shri_i64(t1, t1, 16);
> +
> +        tcg_gen_andi_i64(cpu_mmr[rd], cpu_mmr[rd], mask3);
> +        tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t0);
> +        tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t1);
> +
> +        tcg_temp_free(t0);
> +        tcg_temp_free(t1);
> +    } else {
> +        TCGv_i64 t0 = tcg_temp_new();
> +        TCGv_i64 t1 = tcg_temp_new();
> +        uint64_t mask0 = (1ULL << 16) - 1;
> +        uint64_t mask1 = mask0 << 16;
> +        uint64_t mask2 = mask1 << 16;
> +        uint64_t mask3 = mask2 << 16;

The last two lines are clearer this way:

        uint64_t mask2 = mask0 << 32;
        uint64_t mask3 = mask0 << 48;

> +
> +        tcg_gen_andi_i64(t0, cpu_gpr[rt], mask3);
> +        tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2);
> +        tcg_gen_shri_i64(t1, t1, 16);
> +        tcg_gen_or_i64(t0, t0, t1);
> +        tcg_gen_andi_i64(t1, cpu_gpr[rt], mask1);
> +        tcg_gen_shli_i64(t1, t1, 16);
> +        tcg_gen_or_i64(t0, t0, t1);
> +        tcg_gen_andi_i64(t1, cpu_gpr[rt], mask0);
> +        tcg_gen_or_i64(t0, t0, t1);
> +
> +        tcg_gen_mov_i64(cpu_gpr[rd], t0);
> +
> +        tcg_gen_andi_i64(t0, cpu_mmr[rt], mask3);
> +        tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2);
> +        tcg_gen_shri_i64(t1, t1, 16);
> +        tcg_gen_or_i64(t0, t0, t1);
> +        tcg_gen_andi_i64(t1, cpu_mmr[rt], mask1);
> +        tcg_gen_shli_i64(t1, t1, 16);
> +        tcg_gen_or_i64(t0, t0, t1);
> +        tcg_gen_andi_i64(t1, cpu_mmr[rt], mask0);
> +        tcg_gen_or_i64(t0, t0, t1);
> +
> +        tcg_gen_mov_i64(cpu_mmr[rd], t0);
> +
> +        tcg_temp_free(t0);
> +        tcg_temp_free(t1);
> +    }
> +}
> +
>  #endif
>
>
> @@ -27540,7 +27633,6 @@ static void decode_mmi3(CPUMIPSState *env, 
> DisasContext *ctx)
>      case MMI_OPC_3_PDIVUW:     /* TODO: MMI_OPC_3_PDIVUW */
>      case MMI_OPC_3_POR:        /* TODO: MMI_OPC_3_POR */
>      case MMI_OPC_3_PNOR:       /* TODO: MMI_OPC_3_PNOR */
> -    case MMI_OPC_3_PEXCH:      /* TODO: MMI_OPC_3_PEXCH */
>      case MMI_OPC_3_PEXCW:      /* TODO: MMI_OPC_3_PEXCW */
>          generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
>          break;
> @@ -27550,6 +27642,9 @@ static void decode_mmi3(CPUMIPSState *env, 
> DisasContext *ctx)
>      case MMI_OPC_3_PCPYUD:
>          gen_mmi_pcpyud(ctx);
>          break;
> +    case MMI_OPC_3_PEXCH:
> +        gen_mmi_pexch(ctx);
> +        break;
>      default:
>          MIPS_INVAL("TX79 MMI class MMI3");
>          generate_exception_end(ctx, EXCP_RI);
> --

Apart from minor hints above:

Reviewed-by: Aleksandar Markovic <address@hidden>

> 2.7.4
>
>

________________________________________
From: Mateja Marjanovic <address@hidden>
Sent: Monday, March 4, 2019 4:13:16 PM
To: address@hidden
Cc: address@hidden; Aleksandar Markovic; Aleksandar Rikalo
Subject: [PATCH v3 04/13] target/mips: Add emulation of MMI instruction PEXCH

From: Mateja Marjanovic <address@hidden>

Add emulation of MMI instruction PEXCH. The emulation is implemented
using TCG front end operations directly to achieve better performance.

Signed-off-by: Mateja Marjanovic <address@hidden>
---
 target/mips/translate.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 96 insertions(+), 1 deletion(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4763e06..9472477 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24488,6 +24488,99 @@ static void gen_mmi_pcpyud(DisasContext *ctx)
     }
 }

+/*
+ *  PEXCH rd, rt
+ *
+ *  Parallel Exchange Center Halfword
+ *
+ *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ *  +-----------+---------+---------+---------+---------+-----------+
+ *  |    MMI    |0 0 0 0 0|   rt    |   rd    |  PEXCH  |    MMI3   |
+ *  +-----------+---------+---------+---------+---------+-----------+
+ */
+static void gen_mmi_pexch(DisasContext *ctx)
+{
+    uint32_t pd, rt, rd;
+    uint32_t opcode;
+
+    opcode = ctx->opcode;
+
+    pd = extract32(opcode, 21, 5);
+    rt = extract32(opcode, 16, 5);
+    rd = extract32(opcode, 11, 5);
+
+    if (unlikely(pd != 0)) {
+        generate_exception_end(ctx, EXCP_RI);
+    } else if (rd == 0) {
+        /* nop */
+    } else if (rt == 0) {
+        tcg_gen_movi_i64(cpu_gpr[rd], 0);
+        tcg_gen_movi_i64(cpu_mmr[rd], 0);
+    } else if (rd == rt) {
+        TCGv_i64 t0 = tcg_temp_new();
+        TCGv_i64 t1 = tcg_temp_new();
+        uint64_t mask0 = (1ULL << 16) - 1;
+        uint64_t mask1 = mask0 << 16;
+        uint64_t mask2 = mask1 << 16;
+        uint64_t mask3 = (mask2 << 16) | mask0;
+
+        tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
+        tcg_gen_shli_i64(t0, t0, 16);
+        tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2);
+        tcg_gen_shri_i64(t1, t1, 16);
+
+        tcg_gen_andi_i64(cpu_gpr[rd], cpu_gpr[rd], mask3);
+        tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t0);
+        tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t1);
+
+        tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1);
+        tcg_gen_shli_i64(t0, t0, 16);
+        tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2);
+        tcg_gen_shri_i64(t1, t1, 16);
+
+        tcg_gen_andi_i64(cpu_mmr[rd], cpu_mmr[rd], mask3);
+        tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t0);
+        tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t1);
+
+        tcg_temp_free(t0);
+        tcg_temp_free(t1);
+    } else {
+        TCGv_i64 t0 = tcg_temp_new();
+        TCGv_i64 t1 = tcg_temp_new();
+        uint64_t mask0 = (1ULL << 16) - 1;
+        uint64_t mask1 = mask0 << 16;
+        uint64_t mask2 = mask1 << 16;
+        uint64_t mask3 = mask2 << 16;
+
+        tcg_gen_andi_i64(t0, cpu_gpr[rt], mask3);
+        tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2);
+        tcg_gen_shri_i64(t1, t1, 16);
+        tcg_gen_or_i64(t0, t0, t1);
+        tcg_gen_andi_i64(t1, cpu_gpr[rt], mask1);
+        tcg_gen_shli_i64(t1, t1, 16);
+        tcg_gen_or_i64(t0, t0, t1);
+        tcg_gen_andi_i64(t1, cpu_gpr[rt], mask0);
+        tcg_gen_or_i64(t0, t0, t1);
+
+        tcg_gen_mov_i64(cpu_gpr[rd], t0);
+
+        tcg_gen_andi_i64(t0, cpu_mmr[rt], mask3);
+        tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2);
+        tcg_gen_shri_i64(t1, t1, 16);
+        tcg_gen_or_i64(t0, t0, t1);
+        tcg_gen_andi_i64(t1, cpu_mmr[rt], mask1);
+        tcg_gen_shli_i64(t1, t1, 16);
+        tcg_gen_or_i64(t0, t0, t1);
+        tcg_gen_andi_i64(t1, cpu_mmr[rt], mask0);
+        tcg_gen_or_i64(t0, t0, t1);
+
+        tcg_gen_mov_i64(cpu_mmr[rd], t0);
+
+        tcg_temp_free(t0);
+        tcg_temp_free(t1);
+    }
+}
+
 #endif


@@ -27540,7 +27633,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext 
*ctx)
     case MMI_OPC_3_PDIVUW:     /* TODO: MMI_OPC_3_PDIVUW */
     case MMI_OPC_3_POR:        /* TODO: MMI_OPC_3_POR */
     case MMI_OPC_3_PNOR:       /* TODO: MMI_OPC_3_PNOR */
-    case MMI_OPC_3_PEXCH:      /* TODO: MMI_OPC_3_PEXCH */
     case MMI_OPC_3_PEXCW:      /* TODO: MMI_OPC_3_PEXCW */
         generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
         break;
@@ -27550,6 +27642,9 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext 
*ctx)
     case MMI_OPC_3_PCPYUD:
         gen_mmi_pcpyud(ctx);
         break;
+    case MMI_OPC_3_PEXCH:
+        gen_mmi_pexch(ctx);
+        break;
     default:
         MIPS_INVAL("TX79 MMI class MMI3");
         generate_exception_end(ctx, EXCP_RI);
--
2.7.4