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[Qemu-devel] [PATCH v3 12/13] target/mips: Add emulation of MMI instruct
From: |
Mateja Marjanovic |
Subject: |
[Qemu-devel] [PATCH v3 12/13] target/mips: Add emulation of MMI instruction PEXTUH |
Date: |
Mon, 4 Mar 2019 16:13:24 +0100 |
From: Mateja Marjanovic <address@hidden>
Add emulation of MMI instruction PEXTUH. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <address@hidden>
---
target/mips/translate.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 69 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1bd5ef2..da3fcad 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -25085,6 +25085,72 @@ static void gen_mmi_pextub(DisasContext *ctx)
}
}
+/*
+ * PEXTUH rd, rs, rt
+ *
+ * Parallel Extend Upper from Halfword
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI | rs | rt | rd | PEXTUH | MMI1 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+
+static void gen_mmi_pextuh(DisasContext *ctx)
+{
+ uint32_t rs, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ rs = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (rd == 0) {
+ /* nop */
+ } else {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask = (1ULL << 16) - 1;
+
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask <<= 16;
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask <<= 16;
+
+ tcg_gen_mov_i64(cpu_mmr[rd], t1);
+ tcg_gen_movi_i64(t1, 0);
+
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask <<= 16;
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask <<= 16;
+
+ tcg_gen_mov_i64(cpu_gpr[rd], t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+}
+
#endif
@@ -28077,7 +28143,6 @@ static void decode_mmi1(CPUMIPSState *env, DisasContext
*ctx)
case MMI_OPC_1_PEXTUW: /* TODO: MMI_OPC_1_PEXTUW */
case MMI_OPC_1_PADDUH: /* TODO: MMI_OPC_1_PADDUH */
case MMI_OPC_1_PSUBUH: /* TODO: MMI_OPC_1_PSUBUH */
- case MMI_OPC_1_PEXTUH: /* TODO: MMI_OPC_1_PEXTUH */
case MMI_OPC_1_PADDUB: /* TODO: MMI_OPC_1_PADDUB */
case MMI_OPC_1_PSUBUB: /* TODO: MMI_OPC_1_PSUBUB */
case MMI_OPC_1_QFSRV: /* TODO: MMI_OPC_1_QFSRV */
@@ -28086,6 +28151,9 @@ static void decode_mmi1(CPUMIPSState *env, DisasContext
*ctx)
case MMI_OPC_1_PEXTUB:
gen_mmi_pextub(ctx);
break;
+ case MMI_OPC_1_PEXTUH:
+ gen_mmi_pextuh(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI1");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
- [Qemu-devel] [PATCH v3 00/13] target/mips: Add emulation of data communication MMI instructions, Mateja Marjanovic, 2019/03/04
- [Qemu-devel] [PATCH v3 05/13] target/mips: Add emulation of MMI instruction PEXCW, Mateja Marjanovic, 2019/03/04
- [Qemu-devel] [PATCH v3 02/13] target/mips: Add emulation of MMI instruction PCPYLD, Mateja Marjanovic, 2019/03/04
- [Qemu-devel] [PATCH v3 12/13] target/mips: Add emulation of MMI instruction PEXTUH,
Mateja Marjanovic <=
- [Qemu-devel] [PATCH v3 11/13] target/mips: Add emulation of MMI instruction PEXTUB, Mateja Marjanovic, 2019/03/04
- [Qemu-devel] [PATCH v3 03/13] target/mips: Add emulation of MMI instruction PCPYUD, Mateja Marjanovic, 2019/03/04
- [Qemu-devel] [PATCH v3 04/13] target/mips: Add emulation of MMI instruction PEXCH, Mateja Marjanovic, 2019/03/04
- [Qemu-devel] [PATCH v3 08/13] target/mips: Add emulation of MMI instruction PEXTLB, Mateja Marjanovic, 2019/03/04
- [Qemu-devel] [PATCH v3 07/13] target/mips: Add emulation of MMI instruction PEXEW, Mateja Marjanovic, 2019/03/04
- [Qemu-devel] [PATCH v3 10/13] target/mips: Add emulation of MMI instruction PEXTLW, Mateja Marjanovic, 2019/03/04
- [Qemu-devel] [PATCH v3 01/13] target/mips: Add emulation of MMI instruction PCPYH, Mateja Marjanovic, 2019/03/04