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[Qemu-devel] [PATCH v8 15/38] target/mips: Placeholder for R5900 MMI2 in
From: |
Fredrik Noring |
Subject: |
[Qemu-devel] [PATCH v8 15/38] target/mips: Placeholder for R5900 MMI2 instruction subclass |
Date: |
Sun, 21 Oct 2018 17:37:06 +0200 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
Signed-off-by: Fredrik Noring <address@hidden>
---
target/mips/translate.c | 40 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 28137cdaf4..e5ac9f17e0 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24491,6 +24491,42 @@ static void decode_tx79_mmi1(CPUMIPSState *env,
DisasContext *ctx)
}
}
+static void decode_tx79_mmi2(CPUMIPSState *env, DisasContext *ctx)
+{
+ uint32_t opc = MASK_TX79_MMI2(ctx->opcode);
+
+ switch (opc) {
+ case TX79_MMI2_PMADDW: /* TODO: TX79_MMI2_PMADDW */
+ case TX79_MMI2_PSLLVW: /* TODO: TX79_MMI2_PSLLVW */
+ case TX79_MMI2_PSRLVW: /* TODO: TX79_MMI2_PSRLVW */
+ case TX79_MMI2_PMSUBW: /* TODO: TX79_MMI2_PMSUBW */
+ case TX79_MMI2_PMFHI: /* TODO: TX79_MMI2_PMFHI */
+ case TX79_MMI2_PMFLO: /* TODO: TX79_MMI2_PMFLO */
+ case TX79_MMI2_PINTH: /* TODO: TX79_MMI2_PINTH */
+ case TX79_MMI2_PMULTW: /* TODO: TX79_MMI2_PMULTW */
+ case TX79_MMI2_PDIVW: /* TODO: TX79_MMI2_PDIVW */
+ case TX79_MMI2_PCPYLD: /* TODO: TX79_MMI2_PCPYLD */
+ case TX79_MMI2_PMADDH: /* TODO: TX79_MMI2_PMADDH */
+ case TX79_MMI2_PHMADH: /* TODO: TX79_MMI2_PHMADH */
+ case TX79_MMI2_PAND: /* TODO: TX79_MMI2_PAND */
+ case TX79_MMI2_PXOR: /* TODO: TX79_MMI2_PXOR */
+ case TX79_MMI2_PMSUBH: /* TODO: TX79_MMI2_PMSUBH */
+ case TX79_MMI2_PHMSBH: /* TODO: TX79_MMI2_PHMSBH */
+ case TX79_MMI2_PEXEH: /* TODO: TX79_MMI2_PEXEH */
+ case TX79_MMI2_PREVH: /* TODO: TX79_MMI2_PREVH */
+ case TX79_MMI2_PMULTH: /* TODO: TX79_MMI2_PMULTH */
+ case TX79_MMI2_PDIVBW: /* TODO: TX79_MMI2_PDIVBW */
+ case TX79_MMI2_PEXEW: /* TODO: TX79_MMI2_PEXEW */
+ case TX79_MMI2_PROT3W: /* TODO: TX79_MMI2_PROT3W */
+ generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_MMI_CLASS_MMI2 */
+ break;
+ default:
+ MIPS_INVAL("TX79 MMI class MMI2");
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+}
+
static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_TX79_MMI(ctx->opcode);
@@ -24502,10 +24538,12 @@ static void decode_tx79_mmi(CPUMIPSState *env,
DisasContext *ctx)
case TX79_MMI_CLASS_MMI1:
decode_tx79_mmi1(env, ctx);
break;
+ case TX79_MMI_CLASS_MMI2:
+ decode_tx79_mmi2(env, ctx);
+ break;
case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */
case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */
case TX79_MMI_PLZCW: /* TODO: TX79_MMI_PLZCW */
- case TX79_MMI_CLASS_MMI2: /* TODO: TX79_MMI_CLASS_MMI2 */
case TX79_MMI_MFHI1: /* TODO: TX79_MMI_MFHI1 */
case TX79_MMI_MTHI1: /* TODO: TX79_MMI_MTHI1 */
case TX79_MMI_MFLO1: /* TODO: TX79_MMI_MFLO1 */
--
2.18.1
- [Qemu-devel] [PATCH v8 05/38] target/mips: Define R5900 MMI{0, 1, 2, 3} subclasses and MMI opcode constants, (continued)
- [Qemu-devel] [PATCH v8 05/38] target/mips: Define R5900 MMI{0, 1, 2, 3} subclasses and MMI opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 06/38] target/mips: Define R5900 MMI0 opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 08/38] target/mips: Define R5900 MMI2 opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 07/38] target/mips: Define R5900 MMI1 opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 09/38] target/mips: Define R5900 MMI3 opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 10/38] target/mips: Placeholder for R5900 MMI SQ, handle user mode RDHWR, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 11/38] target/mips: Placeholder for R5900 MMI LQ, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 12/38] target/mips: Placeholder for R5900 MMI instruction class, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 13/38] target/mips: Placeholder for R5900 MMI0 instruction subclass, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 14/38] target/mips: Placeholder for R5900 MMI1 instruction subclass, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 15/38] target/mips: Placeholder for R5900 MMI2 instruction subclass,
Fredrik Noring <=
- [Qemu-devel] [PATCH v8 16/38] target/mips: Placeholder for R5900 MMI3 instruction subclass, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 17/38] target/mips: Support R5900 three-operand MULT and MULTU, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 18/38] target/mips: Support R5900 three-operand MULT1 and MULTU1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 19/38] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 20/38] target/mips: Support R5900 DIV1 and DIVU1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 21/38] target/mips: Support R5900 MOVN, MOVZ and PREF from MIPS IV, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 22/38] target/mips: Support R5900 three-operand MADD and MADD1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 23/38] target/mips: Support R5900 three-operand MADDU and MADDU1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 24/38] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 25/38] tests/tcg/mips: Test R5900 three-operand MULT, Fredrik Noring, 2018/10/21