[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v8 11/38] target/mips: Placeholder for R5900 MMI LQ
From: |
Fredrik Noring |
Subject: |
[Qemu-devel] [PATCH v8 11/38] target/mips: Placeholder for R5900 MMI LQ |
Date: |
Sun, 21 Oct 2018 17:35:56 +0200 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
Signed-off-by: Fredrik Noring <address@hidden>
---
target/mips/translate.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 19a8abad54..2318116d31 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24420,6 +24420,11 @@ static void decode_opc_special3_legacy(CPUMIPSState
*env, DisasContext *ctx)
}
}
+static void decode_tx79_lq(CPUMIPSState *env, DisasContext *ctx)
+{
+ generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_LQ */
+}
+
static void gen_tx79_sq(DisasContext *ctx, int base, int rt, int offset)
{
generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_SQ */
@@ -26425,8 +26430,12 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case OPC_MSA: /* OPC_MDMX */
- /* MDMX: Not implemented. */
- gen_msa(env, ctx);
+ if (ctx->insn_flags & INSN_R5900) {
+ decode_tx79_lq(env, ctx); /* TX79_LQ */
+ } else {
+ /* MDMX: Not implemented. */
+ gen_msa(env, ctx);
+ }
break;
case OPC_PCREL:
check_insn(ctx, ISA_MIPS32R6);
--
2.18.1
- [Qemu-devel] [PATCH v8 01/38] target/mips: Define R5900 instructions and CPU preprocessor constants, (continued)
- [Qemu-devel] [PATCH v8 01/38] target/mips: Define R5900 instructions and CPU preprocessor constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 02/38] disas/mips: Define R5900 disassembly constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 03/38] target/mips: R5900 Multimedia Instruction overview note, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 04/38] target/mips: Define R5900 MMI class, and LQ and SQ opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 05/38] target/mips: Define R5900 MMI{0, 1, 2, 3} subclasses and MMI opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 06/38] target/mips: Define R5900 MMI0 opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 08/38] target/mips: Define R5900 MMI2 opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 07/38] target/mips: Define R5900 MMI1 opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 09/38] target/mips: Define R5900 MMI3 opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 10/38] target/mips: Placeholder for R5900 MMI SQ, handle user mode RDHWR, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 11/38] target/mips: Placeholder for R5900 MMI LQ,
Fredrik Noring <=
- [Qemu-devel] [PATCH v8 12/38] target/mips: Placeholder for R5900 MMI instruction class, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 13/38] target/mips: Placeholder for R5900 MMI0 instruction subclass, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 14/38] target/mips: Placeholder for R5900 MMI1 instruction subclass, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 15/38] target/mips: Placeholder for R5900 MMI2 instruction subclass, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 16/38] target/mips: Placeholder for R5900 MMI3 instruction subclass, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 17/38] target/mips: Support R5900 three-operand MULT and MULTU, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 18/38] target/mips: Support R5900 three-operand MULT1 and MULTU1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 19/38] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 20/38] target/mips: Support R5900 DIV1 and DIVU1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 21/38] target/mips: Support R5900 MOVN, MOVZ and PREF from MIPS IV, Fredrik Noring, 2018/10/21