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[Qemu-devel] [PATCH v8 21/38] target/mips: Support R5900 MOVN, MOVZ and
From: |
Fredrik Noring |
Subject: |
[Qemu-devel] [PATCH v8 21/38] target/mips: Support R5900 MOVN, MOVZ and PREF from MIPS IV |
Date: |
Sun, 21 Oct 2018 17:39:17 +0200 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
The R5900 is taken to be MIPS III with certain modifications. From
MIPS IV it implements the instructions MOVN, MOVZ and PREF.
Signed-off-by: Fredrik Noring <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
---
target/mips/translate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e2ac401d42..1f3dc3d406 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -23552,7 +23552,7 @@ static void decode_opc_special_legacy(CPUMIPSState
*env, DisasContext *ctx)
case OPC_MOVN: /* Conditional move */
case OPC_MOVZ:
check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
- INSN_LOONGSON2E | INSN_LOONGSON2F);
+ INSN_LOONGSON2E | INSN_LOONGSON2F | INSN_R5900);
gen_cond_move(ctx, op1, rd, rs, rt);
break;
case OPC_MFHI: /* Move from HI/LO */
@@ -26388,7 +26388,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
break;
case OPC_PREF:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
+ INSN_R5900);
/* Treat as NOP. */
break;
--
2.18.1
- [Qemu-devel] [PATCH v8 11/38] target/mips: Placeholder for R5900 MMI LQ, (continued)
- [Qemu-devel] [PATCH v8 11/38] target/mips: Placeholder for R5900 MMI LQ, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 12/38] target/mips: Placeholder for R5900 MMI instruction class, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 13/38] target/mips: Placeholder for R5900 MMI0 instruction subclass, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 14/38] target/mips: Placeholder for R5900 MMI1 instruction subclass, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 15/38] target/mips: Placeholder for R5900 MMI2 instruction subclass, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 16/38] target/mips: Placeholder for R5900 MMI3 instruction subclass, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 17/38] target/mips: Support R5900 three-operand MULT and MULTU, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 18/38] target/mips: Support R5900 three-operand MULT1 and MULTU1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 19/38] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 20/38] target/mips: Support R5900 DIV1 and DIVU1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 21/38] target/mips: Support R5900 MOVN, MOVZ and PREF from MIPS IV,
Fredrik Noring <=
- [Qemu-devel] [PATCH v8 22/38] target/mips: Support R5900 three-operand MADD and MADD1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 23/38] target/mips: Support R5900 three-operand MADDU and MADDU1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 24/38] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 25/38] tests/tcg/mips: Test R5900 three-operand MULT, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 27/38] tests/tcg/mips: Test R5900 three-operand MULT1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 26/38] tests/tcg/mips: Test R5900 three-operand MULTU, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 28/38] tests/tcg/mips: Test R5900 three-operand MULTU1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 29/38] tests/tcg/mips: Test R5900 MFLO1 and MFHI1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 30/38] tests/tcg/mips: Test R5900 MTLO1 and MTHI1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 31/38] tests/tcg/mips: Test R5900 DIV1, Fredrik Noring, 2018/10/21