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Re: [Qemu-devel] [PATCH 0/2] sd: sdhci: correct transfer mode register u
From: |
P J P |
Subject: |
Re: [Qemu-devel] [PATCH 0/2] sd: sdhci: correct transfer mode register usage |
Date: |
Mon, 6 Feb 2017 13:25:22 +0530 (IST) |
+-- On Tue, 31 Jan 2017, P J P wrote --+
| In SDHCI emulation, the 'Block Count Enable' bit of the Transfer Mode
| register is used to control 's->blkcnt' value. One, this bit is not
| relevant in single block transfers. Second, Transfer Mode register
| value could be set such that 's->blkcnt' would not see an update
| during multi block transfers. Thus leading to an infinite loop.
|
| This patch set attempts to correct 'Block Count Enable' bit usage.
|
| Thank you.
| --
| Prasad J Pandit (2):
| sd: sdhci: check transfer mode register in multi block transfer
| sd: sdhci: block count enable not relevant in single block transfer
Ping...!
--
Prasad J Pandit / Red Hat Product Security Team
47AF CE69 3A90 54AA 9045 1053 DD13 3D32 FE5B 041F
- Re: [Qemu-devel] [PATCH 0/2] sd: sdhci: correct transfer mode register usage,
P J P <=