Re: [Qemu-devel] [PATCH 0/2] sd: sdhci: correct transfer mode register usage

[Peter Maydell]

On 31 January 2017 at 12:24, P J P <address@hidden> wrote:
> From: Prasad J Pandit <address@hidden>
>
> Hello,
>
> In SDHCI emulation, the 'Block Count Enable' bit of the Transfer Mode
> register is used to control 's->blkcnt' value. One, this bit is not
> relevant in single block transfers. Second, Transfer Mode register
> value could be set such that 's->blkcnt' would not see an update
> during multi block transfers. Thus leading to an infinite loop.
>
> This patch set attempts to correct 'Block Count Enable' bit usage.

Edgar, Alistair: the zynq models are our major SDHCI user -- would
you like to have a look at this patchset, please?

thanks
-- PMM