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From: | Klaus Rudolph |
Subject: | Re: [Simulavr-devel] simulavrxx timers |
Date: | Fri, 30 May 2008 16:42:32 +0200 |
User-agent: | Thunderbird 2.0.0.14 (Windows/20080421) |
Michael Hennebry schrieb:
On Fri, 30 May 2008, Klaus Rudolph wrote:Michael Hennebry schrieb:In HWMegaTimer0::CpuCycle(), there is an 8-case switch (tccr) statement. Its cases are the possible clock select values. Is that correct?Right!tccr contains more than the CS bits,Right! Rest of bits will compared in TimerCompareAfterCount();In HWMegaTimer0::CpuCycle(), why tccr and not tccr & 7?
My version has: unsigned int HWMegaTimer0::CpuCycle(){ switch (tccr & 0x07) { // CS00..CS02 ????
As written, the switch is usually, i.e. whenever 0 != tccr & ~7, a noop. Also, is ASSR on your todo list?
I have actual no TODO-List because I have no avr project to do. Regards Klaus
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