On 30/01/2023 18.31, Harold Grovesteen wrote:
While doing some testing, I encountered the situation where an odd
address is introduced into the active PSW by means of a BC
The odd address is used by Qemu for successful instruction
Do you have, by any chance, a small test program that allows to
the wrong behavior?
I am using qemu-7.2.0-rc4. I have noticed in this list some patches
or about 9 Jan 2023 related to displacement addresses and the
introduction of "gen_psw_addr_disp". The version of qemu I am using
does not contain that function, so I can not validate whether it
addresses the odd instruction address I encountered in my testing.
I assume that's this patch here:
... it hasn't been merged yet, I think, but it also doesn't look like
is any code in there to deal with odd addresses, as far as I can see
first quick glance.
z/Architecture Principles of Operation manual -13 on page 5-13
"A specification exception due to an odd branch address and access
exceptions due to fetching of the instruction at the branch
are not recognized as part of the branch operation but instead are
recognized as exceptions associated with the execution of the
instruction at the branch location."
The specification exception was not recognized at all. Rather the
instruction coded at the odd address, LGFI, was fetched and
It was not until the X'00', also at an odd address, immediately
following the LGFI was itself fetched for execution that the
ceased operation with an operation exception program interrupt.
I am hoping that this is sufficient information to determine if
a known reaction by Qemu to this condition and whether the new
will address this. If neither is the case, FYI.
If you require details, please contact me here or off list.