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From: | liweiwei |
Subject: | Re: [PATCH 2/5] target/riscv: Use sign-extended data address when xl = 32 |
Date: | Tue, 28 Mar 2023 11:07:22 +0800 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 |
On 2023/3/27 18:00, Weiwei Li wrote:
Currently, the pc use signed-extend(in gen_set_pc*) when xl = 32. And data address should use the same memory address space with it when xl = 32. So we should change their address calculation to use sign-extended address when xl = 32.Incorrect. PC sign-extend is mandated by the spec. It can be seen for gdb or the OS. But for the memory address for xl = 32, it's the qemu internal implementation.
Yeah, there is no spec description for the memory address for xlen = 32. But it seemsĀ easier to use the original (sign-extended) pc in this case.
We needn't cut the pc in cpu_get_tb_cpu_state and sign-extend it in riscv_cpu_synchronize_from_tb.
Regards,
Weiwei Li
We should not to make it too complex.
Even for the PC, when fectch instruction, we only use the low 32-bits, as you can seeĀ from the cpu_get_tb_cpu_state.
*pc = cpu_get_xl(env) == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;Zhiwei
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> --- target/riscv/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index bf0e2d318e..c48cb19389 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -570,7 +570,7 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm) tcg_gen_addi_tl(addr, src1, imm); if (get_xl(ctx) == MXL_RV32) { - tcg_gen_ext32u_tl(addr, addr); + tcg_gen_ext32s_tl(addr, addr); } if (ctx->pm_mask_enabled) { @@ -592,7 +592,7 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) tcg_gen_add_tl(addr, src1, offs); if (get_xl(ctx) == MXL_RV32) { - tcg_gen_ext32u_tl(addr, addr); + tcg_gen_ext32s_tl(addr, addr); } if (ctx->pm_mask_enabled) {
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