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qemu-riscv (date)
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Last Modified: Tue Mar 28 2023 23:24:13 -0400
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March 28, 2023
[PATCH v2 2/5] target/riscv: Update cur_pmmask/base when xl changes
,
Weiwei Li
,
23:24
[PATCH v2 4/5] target/riscv: Add support for PC-relative translation
,
Weiwei Li
,
23:24
[PATCH v2 3/5] target/riscv: Sync cpu_pc before update badaddr
,
Weiwei Li
,
23:24
[PATCH v2 0/5] target/riscv: Fix pointer mask related support
,
Weiwei Li
,
23:24
[PATCH v2 5/5] target/riscv: Add pointer mask support for instruction fetch
,
Weiwei Li
,
23:24
[PATCH v2 1/5] target/riscv: Fix pointer mask transformation for vector address
,
Weiwei Li
,
23:24
[PATCH] target/riscv: Fix Guest Physical Address Translation
,
Irina Ryapolova
,
13:53
[PATCH v5 9/9] target/riscv: rework write_misa()
,
Daniel Henrique Barboza
,
13:36
[PATCH v5 8/9] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
,
Daniel Henrique Barboza
,
13:36
[PATCH v5 7/9] target/riscv/cpu.c: validate extensions before riscv_timer_init()
,
Daniel Henrique Barboza
,
13:36
[PATCH v5 6/9] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
,
Daniel Henrique Barboza
,
13:36
[PATCH v5 5/9] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers
,
Daniel Henrique Barboza
,
13:36
[PATCH v5 4/9] target/riscv: add PRIV_VERSION_LATEST
,
Daniel Henrique Barboza
,
13:36
[PATCH v5 3/9] target/riscv/cpu.c: remove set_priv_version()
,
Daniel Henrique Barboza
,
13:36
[PATCH v5 2/9] target/riscv/cpu.c: remove set_vext_version()
,
Daniel Henrique Barboza
,
13:36
[PATCH v5 1/9] target/riscv/cpu.c: add riscv_cpu_validate_v()
,
Daniel Henrique Barboza
,
13:35
[PATCH v5 0/9] target/riscv: rework CPU extensions validation
,
Daniel Henrique Barboza
,
13:35
Re: [PATCH for-8.1 v4 18/25] target/riscv: error out on priv failure for RVH
,
Daniel Henrique Barboza
,
10:33
Re: [PATCH v11 4/5] target/riscv: smstateen check for fcsr
,
Mayuresh Chitale
,
07:07
Re: [PATCH 1/5] target/riscv: Fix effective address for pointer mask
,
liweiwei
,
06:26
Re: [PATCH 1/5] target/riscv: Fix effective address for pointer mask
,
LIU Zhiwei
,
03:25
Re: [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch
,
liweiwei
,
00:09
March 27, 2023
Re: [PATCH 1/5] target/riscv: Fix effective address for pointer mask
,
liweiwei
,
23:33
Re: [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch
,
Richard Henderson
,
23:31
Re: [PATCH 1/5] target/riscv: Fix effective address for pointer mask
,
LIU Zhiwei
,
23:24
Re: [PATCH 1/5] target/riscv: Fix effective address for pointer mask
,
Richard Henderson
,
23:18
Re: [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch
,
liweiwei
,
23:14
Re: [PATCH 2/5] target/riscv: Use sign-extended data address when xl = 32
,
liweiwei
,
23:07
Re: [PATCH 1/5] target/riscv: Fix effective address for pointer mask
,
liweiwei
,
22:49
Re: [PATCH v6 07/25] target/riscv: Reduce overhead of MSTATUS_SUM change
,
LIU Zhiwei
,
22:41
Re: [PATCH v6 06/25] target/riscv: Separate priv from mmu_idx
,
LIU Zhiwei
,
22:39
Re: [PATCH v6 04/25] target/riscv: Remove mstatus_hs_{fs,vs} from tb_flags
,
LIU Zhiwei
,
22:34
Re: [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch
,
LIU Zhiwei
,
22:31
Re: [PATCH 4/5] target/riscv: take xl into consideration for vector address
,
LIU Zhiwei
,
22:22
Re: [PATCH 3/5] target/riscv: Fix pointer mask transformation for vector address
,
LIU Zhiwei
,
22:21
Re: [PATCH 1/5] target/riscv: Fix effective address for pointer mask
,
LIU Zhiwei
,
22:20
Re: [PATCH 2/5] target/riscv: Use sign-extended data address when xl = 32
,
LIU Zhiwei
,
22:14
Re: [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch
,
liweiwei
,
21:56
Re: [PATCH v6 13/25] target/riscv: Introduce mmuidx_priv
,
LIU Zhiwei
,
21:33
Re: [PATCH v6 00/25] target/riscv: MSTATUS_SUM + cleanups
,
Wu, Fei
,
21:22
Re: [PATCH v2 06/10] target/riscv: Remove riscv_cpu_virt_enabled()
,
LIU Zhiwei
,
21:15
[PATCH v2 19/19] target/riscv/cpu.c: redesign register_cpu_props()
,
Daniel Henrique Barboza
,
18:51
[PATCH v2 18/19] target/riscv: add RVG and remove cpu->cfg.ext_g
,
Daniel Henrique Barboza
,
18:50
[PATCH v2 17/19] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()
,
Daniel Henrique Barboza
,
18:50
[PATCH v2 16/19] target/riscv: remove riscv_cpu_sync_misa_cfg()
,
Daniel Henrique Barboza
,
18:50
[PATCH v2 15/19] target/riscv: remove cpu->cfg.ext_v
,
Daniel Henrique Barboza
,
18:50
[PATCH v2 14/19] target/riscv: remove cpu->cfg.ext_j
,
Daniel Henrique Barboza
,
18:50
[PATCH v2 12/19] target/riscv: remove cpu->cfg.ext_u
,
Daniel Henrique Barboza
,
18:50
[PATCH v2 11/19] target/riscv: remove cpu->cfg.ext_s
,
Daniel Henrique Barboza
,
18:50
[PATCH v2 13/19] target/riscv: remove cpu->cfg.ext_h
,
Daniel Henrique Barboza
,
18:50
[PATCH v2 08/19] target/riscv: remove cpu->cfg.ext_i
,
Daniel Henrique Barboza
,
18:50
[PATCH v2 09/19] target/riscv: remove cpu->cfg.ext_e
,
Daniel Henrique Barboza
,
18:50
[PATCH v2 10/19] target/riscv: remove cpu->cfg.ext_m
,
Daniel Henrique Barboza
,
18:50
[PATCH v2 07/19] target/riscv: remove cpu->cfg.ext_f
,
Daniel Henrique Barboza
,
18:50
[PATCH v2 06/19] target/riscv: remove cpu->cfg.ext_d
,
Daniel Henrique Barboza
,
18:50
[PATCH v2 05/19] target/riscv: remove cpu->cfg.ext_c
,
Daniel Henrique Barboza
,
18:50
[PATCH v2 04/19] target/riscv: remove cpu->cfg.ext_a
,
Daniel Henrique Barboza
,
18:50
[PATCH v2 03/19] target/riscv: introduce riscv_cpu_add_misa_properties()
,
Daniel Henrique Barboza
,
18:50
[PATCH v2 02/19] target/riscv: remove MISA properties from isa_edata_arr[]
,
Daniel Henrique Barboza
,
18:49
[PATCH v2 01/19] target/riscv: sync env->misa_ext* with cpu->cfg in realize()
,
Daniel Henrique Barboza
,
18:49
[PATCH v2 00/19] remove MISA ext_N flags from cpu->cfg
,
Daniel Henrique Barboza
,
18:49
Re: [PATCH 03/19] target/riscv: introduce riscv_cpu_add_misa_properties()
,
Richard Henderson
,
18:27
Re: [PATCH 03/19] target/riscv: introduce riscv_cpu_add_misa_properties()
,
Daniel Henrique Barboza
,
18:15
Re: [PATCH 03/19] target/riscv: introduce riscv_cpu_add_misa_properties()
,
Daniel Henrique Barboza
,
14:59
Re: [PATCH 03/19] target/riscv: introduce riscv_cpu_add_misa_properties()
,
Richard Henderson
,
14:52
Re: [PATCH 03/19] target/riscv: introduce riscv_cpu_add_misa_properties()
,
Richard Henderson
,
14:43
Re: [PATCH v2 06/10] target/riscv: Remove riscv_cpu_virt_enabled()
,
Richard Henderson
,
14:11
Re: [PATCH v2 05/10] target/riscv: Convert env->virt to a bool env->virt_enabled
,
Richard Henderson
,
14:09
Re: [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch
,
Richard Henderson
,
14:04
Re: [PATCH] riscv: Add support for the Zfa extension
,
Richard Henderson
,
13:18
Re: [PATCH v6 00/25] target/riscv: MSTATUS_SUM + cleanups
,
Daniel Henrique Barboza
,
12:43
Re: [PATCH v6 13/25] target/riscv: Introduce mmuidx_priv
,
Richard Henderson
,
12:29
Re: [PATCH v6 04/25] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags
,
Richard Henderson
,
12:22
Re: [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch
,
Daniel Henrique Barboza
,
11:14
Re: [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch
,
Daniel Henrique Barboza
,
09:29
Re: [PATCH v4 0/3] NUMA: Apply cluster-NUMA-node boundary for aarch64 and riscv machines
,
Igor Mammedov
,
09:27
Re: [PATCH 4/5] target/riscv: take xl into consideration for vector address
,
Daniel Henrique Barboza
,
09:21
Re: [PATCH 3/5] target/riscv: Fix pointer mask transformation for vector address
,
Daniel Henrique Barboza
,
09:20
Re: [PATCH 2/5] target/riscv: Use sign-extended data address when xl = 32
,
Daniel Henrique Barboza
,
09:20
Re: [PATCH 1/5] target/riscv: Fix effective address for pointer mask
,
Daniel Henrique Barboza
,
09:19
[PATCH 19/19] target/riscv/cpu.c: redesign register_cpu_props()
,
Daniel Henrique Barboza
,
08:44
[PATCH 18/19] target/riscv: add RVG and remove cpu->cfg.ext_g
,
Daniel Henrique Barboza
,
08:43
[PATCH 17/19] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()
,
Daniel Henrique Barboza
,
08:43
[PATCH 16/19] target/riscv: remove riscv_cpu_sync_misa_cfg()
,
Daniel Henrique Barboza
,
08:43
[PATCH 15/19] target/riscv: remove cpu->cfg.ext_v
,
Daniel Henrique Barboza
,
08:43
[PATCH 14/19] target/riscv: remove cpu->cfg.ext_j
,
Daniel Henrique Barboza
,
08:43
[PATCH 13/19] target/riscv: remove cpu->cfg.ext_h
,
Daniel Henrique Barboza
,
08:43
[PATCH 12/19] target/riscv: remove cpu->cfg.ext_u
,
Daniel Henrique Barboza
,
08:43
[PATCH 11/19] target/riscv: remove cpu->cfg.ext_s
,
Daniel Henrique Barboza
,
08:43
[PATCH 10/19] target/riscv: remove cpu->cfg.ext_m
,
Daniel Henrique Barboza
,
08:43
[PATCH 09/19] target/riscv: remove cpu->cfg.ext_e
,
Daniel Henrique Barboza
,
08:43
[PATCH 08/19] target/riscv: remove cpu->cfg.ext_i
,
Daniel Henrique Barboza
,
08:43
[PATCH 07/19] target/riscv: remove cpu->cfg.ext_f
,
Daniel Henrique Barboza
,
08:43
[PATCH 06/19] target/riscv: remove cpu->cfg.ext_d
,
Daniel Henrique Barboza
,
08:43
[PATCH 05/19] target/riscv: remove cpu->cfg.ext_c
,
Daniel Henrique Barboza
,
08:43
[PATCH 04/19] target/riscv: remove cpu->cfg.ext_a
,
Daniel Henrique Barboza
,
08:43
[PATCH 03/19] target/riscv: introduce riscv_cpu_add_misa_properties()
,
Daniel Henrique Barboza
,
08:43
[PATCH 02/19] target/riscv: remove MISA properties from isa_edata_arr[]
,
Daniel Henrique Barboza
,
08:43
[PATCH 01/19] target/riscv: sync env->misa_ext* with cpu->cfg in realize()
,
Daniel Henrique Barboza
,
08:43
[PATCH 00/19] remove MISA ext_N flags from cpu->cfg
,
Daniel Henrique Barboza
,
08:42
[PATCH 2/5] target/riscv: Use sign-extended data address when xl = 32
,
Weiwei Li
,
06:01
[PATCH 1/5] target/riscv: Fix effective address for pointer mask
,
Weiwei Li
,
06:01
[PATCH 3/5] target/riscv: Fix pointer mask transformation for vector address
,
Weiwei Li
,
06:01
[PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch
,
Weiwei Li
,
06:01
[PATCH 0/5] target/riscv: Fix pointer mask related support
,
Weiwei Li
,
06:01
[PATCH 4/5] target/riscv: take xl into consideration for vector address
,
Weiwei Li
,
06:01
Re: [PATCH] riscv: Add support for the Zfa extension
,
liweiwei
,
04:41
[PATCH v2 09/10] target/riscv: Fix format for comments
,
Weiwei Li
,
04:15
[PATCH v2 08/10] target/riscv: Fix format for indentation
,
Weiwei Li
,
04:09
[PATCH v2 06/10] target/riscv: Remove riscv_cpu_virt_enabled()
,
Weiwei Li
,
04:09
[PATCH v2 04/10] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled
,
Weiwei Li
,
04:09
[PATCH v2 00/10] target/riscv: Simplification for RVH related check and code style fix
,
Weiwei Li
,
04:09
[PATCH v2 05/10] target/riscv: Convert env->virt to a bool env->virt_enabled
,
Weiwei Li
,
04:09
[PATCH v2 10/10] target/riscv: Fix lines with over 80 characters
,
Weiwei Li
,
04:09
[PATCH v2 03/10] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled
,
Weiwei Li
,
04:09
[PATCH v2 01/10] target/riscv: Remove redundant call to riscv_cpu_virt_enabled
,
Weiwei Li
,
04:09
[PATCH v2 07/10] target/riscv: Remove redundant parentheses
,
Weiwei Li
,
04:09
[PATCH v2 02/10] target/riscv: Remove redundant check on RVH
,
Weiwei Li
,
04:09
[PATCH] riscv: Add support for the Zfa extension
,
Christoph Muellner
,
04:00
March 26, 2023
Re: [PATCH v6 13/25] target/riscv: Introduce mmuidx_priv
,
LIU Zhiwei
,
22:08
Re: [PATCH v6 04/25] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags
,
liweiwei
,
21:35
Re: [PATCH 1/1] target/riscv: Convert env->virt to a bool env->virt_enabled
,
liweiwei
,
10:50
Re: [PATCH v6 00/25] target/riscv: MSTATUS_SUM + cleanups
,
liweiwei
,
10:18
Re: [PATCH v6 02/25] target/riscv: Add a general status enum for extensions
,
liweiwei
,
08:54
Re: [PATCH 6/8] target/riscv: Fix format for indentation
,
liweiwei
,
08:38
Re: [PATCH v6 00/25] target/riscv: MSTATUS_SUM + cleanups
,
Richard Henderson
,
01:17
March 25, 2023
Re: [PATCH 0/8] target/riscv: Simplification for RVH related check and code style fix
,
LIU Zhiwei
,
11:05
[PATCH 1/1] target/riscv: Convert env->virt to a bool env->virt_enabled
,
LIU Zhiwei
,
10:54
Re: [PATCH 6/8] target/riscv: Fix format for indentation
,
LIU Zhiwei
,
10:24
[PATCH v6 25/25] target/riscv: Reorg sum check in get_physical_address
,
Richard Henderson
,
09:49
[PATCH v6 15/25] target/riscv: Move hstatus.spvp check to check_access_hlsv
,
Richard Henderson
,
08:43
[PATCH v6 24/25] target/riscv: Reorg access check in get_physical_address
,
Richard Henderson
,
08:42
[PATCH v6 05/25] target/riscv: Add a tb flags field for vstart
,
Richard Henderson
,
08:42
[PATCH v6 18/25] target/riscv: Hoist second stage mode change to callers
,
Richard Henderson
,
08:07
[PATCH v6 00/25] target/riscv: MSTATUS_SUM + cleanups
,
Richard Henderson
,
08:05
[PATCH v6 04/25] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags
,
Richard Henderson
,
08:04
[PATCH v6 08/25] accel/tcg: Add cpu_ld*_code_mmu
,
Richard Henderson
,
08:04
[PATCH v6 02/25] target/riscv: Add a general status enum for extensions
,
Richard Henderson
,
08:02
[PATCH v6 09/25] target/riscv: Use cpu_ld*_code_mmu for HLVX
,
Richard Henderson
,
08:02
[PATCH v6 01/25] target/riscv: Extract virt enabled state from tb flags
,
Richard Henderson
,
08:02
[PATCH v6 17/25] target/riscv: Check SUM in the correct register
,
Richard Henderson
,
08:01
[PATCH v6 21/25] target/riscv: Suppress pte update with is_debug
,
Richard Henderson
,
08:01
[PATCH v6 14/25] target/riscv: Introduce mmuidx_2stage
,
Richard Henderson
,
07:58
[PATCH v6 13/25] target/riscv: Introduce mmuidx_priv
,
Richard Henderson
,
07:58
[PATCH v6 16/25] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
,
Richard Henderson
,
07:55
[PATCH v6 11/25] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT
,
Richard Henderson
,
07:55
[PATCH v6 19/25] target/riscv: Hoist pbmte and hade out of the level loop
,
Richard Henderson
,
07:54
[PATCH v6 07/25] target/riscv: Reduce overhead of MSTATUS_SUM change
,
Richard Henderson
,
07:53
[PATCH v6 20/25] target/riscv: Move leaf pte processing out of level loop
,
Richard Henderson
,
07:53
[PATCH v6 23/25] target/riscv: Merge checks for reserved pte flags
,
Richard Henderson
,
07:52
[PATCH v6 12/25] target/riscv: Introduce mmuidx_sum
,
Richard Henderson
,
07:52
[PATCH v6 06/25] target/riscv: Separate priv from mmu_idx
,
Richard Henderson
,
07:51
[PATCH v6 22/25] target/riscv: Don't modify SUM with is_debug
,
Richard Henderson
,
07:51
[PATCH v6 10/25] target/riscv: Handle HLV, HSV via helpers
,
Richard Henderson
,
07:50
[PATCH v6 03/25] target/riscv: Encode the FS and VS on a normal way for tb flags
,
Richard Henderson
,
07:49
March 24, 2023
Re: [PATCH 7/8] target/riscv: Fix format for comments
,
Richard Henderson
,
14:12
Re: [PATCH 5/8] target/riscv: Remove redundant parentheses
,
Richard Henderson
,
14:10
Re: [PATCH 4/8] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled
,
Richard Henderson
,
14:10
Re: [PATCH 3/8] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled
,
Richard Henderson
,
14:05
Re: [PATCH 2/8] target/riscv: Remove redundant check on RVH
,
Richard Henderson
,
14:04
Re: [PATCH 1/8] target/riscv: Remove redundant call to riscv_cpu_virt_enabled
,
Richard Henderson
,
14:04
Re: [PATCH v5 1/2] target/riscv: separate priv from mmu_idx
,
Richard Henderson
,
13:57
Re: [PATCH v2 4/4] target/riscv: Add a tb flags field for vstart
,
Richard Henderson
,
13:08
Re: [PATCH v2 3/4] target/riscv: Encode the FS and VS on a normal way for tb flags
,
Richard Henderson
,
13:08
Re: [PATCH v2 2/4] target/riscv: Add a general status enum for extensions
,
Richard Henderson
,
13:07
Re: [PATCH v2 1/4] target/riscv: Extract virt enabled state from tb flags
,
Richard Henderson
,
13:05
Re: [PATCH 4/4] target/riscv: Add a tb flags field for vstart
,
Richard Henderson
,
13:05
Re: [PATCH 3/4] target/riscv: Encode the FS and VS on a normal way for tb flags
,
Richard Henderson
,
13:03
Re: [PATCH 1/4] target/riscv: Extract virt enabled state from tb flags
,
Richard Henderson
,
13:01
Re: [PATCH for-8.1 v4 23/25] target/riscv: rework write_misa()
,
liweiwei
,
11:28
Re: [PATCH for-8.1 v4 22/25] target/riscv: use misa_ext val in riscv_cpu_validate_extensions()
,
liweiwei
,
11:28
Re: [PATCH for-8.1 v4 24/25] target/riscv: update cpu->cfg misa bits in commit_cpu_cfg()
,
liweiwei
,
11:22
Re: [PATCH for-8.1 v4 18/25] target/riscv: error out on priv failure for RVH
,
liweiwei
,
10:56
Re: [PATCH for-8.1 v4 15/25] target/riscv/cpu.c: split RVG code from validate_set_extensions()
,
liweiwei
,
10:48
Re: [PATCH for-8.1 v4 14/25] target/riscv: add RVG
,
liweiwei
,
10:43
Re: [PATCH 2/4] target/riscv: Add a general status enum for extensions
,
LIU Zhiwei
,
09:54
Re: [PATCH] target/riscv: Fix itrigger when icount is used
,
liweiwei
,
09:46
Re: [PATCH v11 4/5] target/riscv: smstateen check for fcsr
,
liweiwei
,
09:32
Re: [PATCH 3/4] target/riscv: Encode the FS and VS on a normal way for tb flags
,
liweiwei
,
09:27
Re: [PATCH v12 00/10] support subsets of code size reduction extension
,
liweiwei
,
09:24
Re: [PATCH v4 1/2] target/riscv: separate priv from mmu_idx
,
Wu, Fei
,
09:22
Re: [PATCH 2/4] target/riscv: Add a general status enum for extensions
,
liweiwei
,
09:11
[PATCH 6/8] target/riscv: Fix format for indentation
,
Weiwei Li
,
09:06
Re: [PATCH 4/4] target/riscv: Add a tb flags field for vstart
,
liweiwei
,
09:05
Re: [PATCH 1/4] target/riscv: Extract virt enabled state from tb flags
,
liweiwei
,
08:48
[PATCH 8/8] target/riscv: Fix lines with over 80 characters
,
Weiwei Li
,
08:45
[PATCH 7/8] target/riscv: Fix format for comments
,
Weiwei Li
,
08:44
[PATCH 4/8] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled
,
Weiwei Li
,
08:41
[PATCH 2/8] target/riscv: Remove redundant check on RVH
,
Weiwei Li
,
08:41
[PATCH 5/8] target/riscv: Remove redundant parentheses
,
Weiwei Li
,
08:41
[PATCH 3/8] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled
,
Weiwei Li
,
08:41
[PATCH 0/8] target/riscv: Simplification for RVH related check and code style fix
,
Weiwei Li
,
08:40
[PATCH 1/8] target/riscv: Remove redundant call to riscv_cpu_virt_enabled
,
Weiwei Li
,
08:40
[PATCH] target/riscv: Fix itrigger when icount is used
,
LIU Zhiwei
,
02:41
[PATCH 3/4] target/riscv: Encode the FS and VS on a normal way for tb flags
,
LIU Zhiwei
,
02:03
[PATCH 4/4] target/riscv: Add a tb flags field for vstart
,
LIU Zhiwei
,
02:03
[PATCH 2/4] target/riscv: Add a general status enum for extensions
,
LIU Zhiwei
,
02:01
[PATCH 0/4] Fix tb flags use
,
LIU Zhiwei
,
02:01
[PATCH 1/4] target/riscv: Extract virt enabled state from tb flags
,
LIU Zhiwei
,
02:01
[PATCH v5 1/2] target/riscv: separate priv from mmu_idx
,
Fei Wu
,
01:41
[PATCH v5 2/2] target/riscv: reduce overhead of MSTATUS_SUM change
,
Fei Wu
,
01:41
[PATCH v5 0/2] target/riscv: reduce MSTATUS_SUM overhead
,
Fei Wu
,
01:40
March 23, 2023
Re: [PATCH v4 1/2] target/riscv: separate priv from mmu_idx
,
Wu, Fei
,
23:05
Re: [PATCH v4 1/2] target/riscv: separate priv from mmu_idx
,
Richard Henderson
,
23:05
Re: [PATCH v4 1/2] target/riscv: separate priv from mmu_idx
,
Wu, Fei
,
21:23
Re: [PATCH v4 1/2] target/riscv: separate priv from mmu_idx
,
Wu, Fei
,
21:21
Re: [PATCH v4 1/2] target/riscv: separate priv from mmu_idx
,
Wu, Fei
,
21:04
Re: [PATCH for-8.1 v4 11/25] target/riscv/cpu.c: set cpu config in set_misa()
,
Daniel Henrique Barboza
,
19:23
Re: [PATCH v3] target/riscv: reduce overhead of MSTATUS_SUM change
,
Richard Henderson
,
12:41
Re: [PATCH v3] target/riscv: reduce overhead of MSTATUS_SUM change
,
Richard Henderson
,
12:11
Re: [PATCH v4 1/2] target/riscv: separate priv from mmu_idx
,
Richard Henderson
,
12:07
Re: [PATCH v4 1/2] target/riscv: separate priv from mmu_idx
,
Richard Henderson
,
11:53
Re: [PATCH v3] target/riscv: reduce overhead of MSTATUS_SUM change
,
Wu, Fei
,
09:45
Re: [PATCH v4 1/2] target/riscv: separate priv from mmu_idx
,
Wu, Fei
,
09:40
Re: [PATCH qemu v3] linux-user: Emulate /proc/cpuinfo output for riscv
,
Laurent Vivier
,
04:14
Re: [PATCH qemu v3] linux-user: Emulate /proc/cpuinfo output for riscv
,
Laurent Vivier
,
03:52
Re: [PATCH v4 1/2] target/riscv: separate priv from mmu_idx
,
LIU Zhiwei
,
02:59
Re: [PATCH v4 1/2] target/riscv: separate priv from mmu_idx
,
Wu, Fei
,
02:26
Re: [PATCH v4 1/2] target/riscv: separate priv from mmu_idx
,
Wu, Fei
,
02:00
Re: [PATCH v4 1/2] target/riscv: separate priv from mmu_idx
,
LIU Zhiwei
,
01:37
March 22, 2023
Re: [PATCH for-8.1 v4 12/25] target/riscv/cpu.c: redesign register_cpu_props()
,
LIU Zhiwei
,
23:23
[PATCH v4 2/2] target/riscv: reduce overhead of MSTATUS_SUM change
,
Fei Wu
,
22:43
[PATCH v4 1/2] target/riscv: separate priv from mmu_idx
,
Fei Wu
,
22:42
[PATCH v4 0/2] target/riscv: reduce MSTATUS_SUM overhead
,
Fei Wu
,
22:42
Re: [PATCH for-8.1 v4 11/25] target/riscv/cpu.c: set cpu config in set_misa()
,
LIU Zhiwei
,
22:18
Re: [PATCH for-8.1 v4 11/25] target/riscv/cpu.c: set cpu config in set_misa()
,
LIU Zhiwei
,
22:15
Re: [PATCH for-8.1 v4 10/25] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions()
,
LIU Zhiwei
,
22:05
Re: [PATCH for-8.1 v4 09/25] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
,
LIU Zhiwei
,
22:03
Re: [PATCH for-8.1 v4 08/25] target/riscv/cpu.c: validate extensions before riscv_timer_init()
,
LIU Zhiwei
,
21:53
Re: [PATCH for-8.1 v4 07/25] target/riscv: move pmp and epmp validations to validate_set_extensions()
,
LIU Zhiwei
,
21:42
Re: [PATCH for-8.1 v4 06/25] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
,
LIU Zhiwei
,
21:36
Re: [PATCH v3] target/riscv: reduce overhead of MSTATUS_SUM change
,
Wu, Fei
,
21:27
Re: [PATCH v3] target/riscv: reduce overhead of MSTATUS_SUM change
,
Wu, Fei
,
20:39
[PATCH for-8.1 v4 20/25] target/riscv: make validate_misa_ext() use a misa_ext val
,
Daniel Henrique Barboza
,
18:58
[PATCH for-8.1 v4 08/25] target/riscv/cpu.c: validate extensions before riscv_timer_init()
,
Daniel Henrique Barboza
,
18:54
[PATCH for-8.1 v4 11/25] target/riscv/cpu.c: set cpu config in set_misa()
,
Daniel Henrique Barboza
,
18:52
[PATCH for-8.1 v4 24/25] target/riscv: update cpu->cfg misa bits in commit_cpu_cfg()
,
Daniel Henrique Barboza
,
18:51
[PATCH for-8.1 v4 14/25] target/riscv: add RVG
,
Daniel Henrique Barboza
,
18:50
[PATCH for-8.1 v4 18/25] target/riscv: error out on priv failure for RVH
,
Daniel Henrique Barboza
,
18:37
[PATCH for-8.1 v4 09/25] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
,
Daniel Henrique Barboza
,
18:32
[PATCH for-8.1 v4 15/25] target/riscv/cpu.c: split RVG code from validate_set_extensions()
,
Daniel Henrique Barboza
,
18:32
[PATCH for-8.1 v4 22/25] target/riscv: use misa_ext val in riscv_cpu_validate_extensions()
,
Daniel Henrique Barboza
,
18:32
[PATCH for-8.1 v4 21/25] target/riscv: split riscv_cpu_validate_set_extensions()
,
Daniel Henrique Barboza
,
18:32
[PATCH for-8.1 v4 10/25] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions()
,
Daniel Henrique Barboza
,
18:32
[PATCH for-8.1 v4 17/25] target/riscv: move riscv_cpu_validate_v() to validate_misa_ext()
,
Daniel Henrique Barboza
,
18:32
[PATCH for-8.1 v4 12/25] target/riscv/cpu.c: redesign register_cpu_props()
,
Daniel Henrique Barboza
,
18:32
[PATCH for-8.1 v4 04/25] target/riscv: add PRIV_VERSION_LATEST
,
Daniel Henrique Barboza
,
18:30
[PATCH for-8.1 v4 03/25] target/riscv/cpu.c: remove set_priv_version()
,
Daniel Henrique Barboza
,
18:30
[PATCH for-8.1 v4 00/25] target/riscv: rework CPU extensions validation
,
Daniel Henrique Barboza
,
18:29
[PATCH for-8.1 v4 02/25] target/riscv/cpu.c: remove set_vext_version()
,
Daniel Henrique Barboza
,
18:28
[PATCH for-8.1 v4 16/25] target/riscv/cpu.c: add riscv_cpu_validate_misa_ext()
,
Daniel Henrique Barboza
,
18:28
[PATCH for-8.1 v4 01/25] target/riscv/cpu.c: add riscv_cpu_validate_v()
,
Daniel Henrique Barboza
,
18:28
[PATCH for-8.1 v4 05/25] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers
,
Daniel Henrique Barboza
,
18:27
[PATCH for-8.1 v4 23/25] target/riscv: rework write_misa()
,
Daniel Henrique Barboza
,
18:26
[PATCH for-8.1 v4 25/25] target/riscv: handle RVG updates in write_misa()
,
Daniel Henrique Barboza
,
18:23
[PATCH for-8.1 v4 19/25] target/riscv: write env->misa_ext* in register_generic_cpu_props()
,
Daniel Henrique Barboza
,
18:21
[PATCH for-8.1 v4 13/25] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers
,
Daniel Henrique Barboza
,
18:21
[PATCH for-8.1 v4 06/25] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
,
Daniel Henrique Barboza
,
18:21
[PATCH for-8.1 v4 07/25] target/riscv: move pmp and epmp validations to validate_set_extensions()
,
Daniel Henrique Barboza
,
18:21
Re: [PATCH for-8.1 v3 25/26] target/riscv: allow write_misa() to enable RVG
,
Daniel Henrique Barboza
,
13:42
Re: [PATCH for-8.1 v3 26/26] target/riscv: allow write_misa() to enable RVV
,
Daniel Henrique Barboza
,
13:39
Re: [PATCH v3] target/riscv: reduce overhead of MSTATUS_SUM change
,
Richard Henderson
,
09:19
Re: [PATCH v3] target/riscv: reduce overhead of MSTATUS_SUM change
,
Wu, Fei
,
09:12
Re: [PATCH v3] target/riscv: reduce overhead of MSTATUS_SUM change
,
liweiwei
,
08:37
[PATCH v3] target/riscv: reduce overhead of MSTATUS_SUM change
,
Fei Wu
,
08:11
Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change
,
Wu, Fei
,
03:05
Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change
,
LIU Zhiwei
,
02:50
Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change
,
Wu, Fei
,
02:41
March 21, 2023
Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change
,
Wu, Fei
,
23:36
Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change
,
Richard Henderson
,
23:31
Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change
,
LIU Zhiwei
,
23:17
Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change
,
Wu, Fei
,
22:47
Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change
,
LIU Zhiwei
,
21:58
[PATCH qemu v3] linux-user: Emulate /proc/cpuinfo output for riscv
,
Afonso Bordado
,
16:19
Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change
,
Richard Henderson
,
12:11
[PATCH v2] target/riscv: reduce overhead of MSTATUS_SUM change
,
Fei Wu
,
09:38
Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change
,
liweiwei
,
09:27
Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change
,
Wu, Fei
,
09:22
Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change
,
liweiwei
,
08:59
Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change
,
liweiwei
,
08:47
Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change
,
Wu, Fei
,
08:01
Re: [PATCH v4 3/3] hw/riscv: Validate cluster and NUMA node boundary
,
Alistair Francis
,
07:41
Re: [PATCH v4 1/3] numa: Validate cluster and NUMA node boundary if required
,
Alistair Francis
,
07:39
Re: [PATCH] target/riscv: Fix priv version dependency for vector and zfh
,
Daniel Henrique Barboza
,
06:01
Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change
,
liweiwei
,
05:48
Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change
,
Wu, Fei
,
05:15
Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change
,
liweiwei
,
04:51
Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change
,
Wu, Fei
,
04:41
Re: [PATCH] target/riscv: reduce overhead of MSTATUS_SUM change
,
liweiwei
,
04:28
[PATCH] target/riscv: reduce overhead of MSTATUS_SUM change
,
fei2 . wu
,
02:36
Re: [PATCH] target/riscv: Fix priv version dependency for vector and zfh
,
liweiwei
,
02:03
Re: [PATCH for-8.1 v3 05/26] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers
,
LIU Zhiwei
,
00:51
[PATCH] target/riscv: Fix priv version dependency for vector and zfh
,
LIU Zhiwei
,
00:34
March 20, 2023
Re: [PATCH for-8.1 v3 11/26] target/riscv/cpu.c: set cpu config in set_misa()
,
liweiwei
,
23:55
Re: [PATCH for-8.1 v3 26/26] target/riscv: allow write_misa() to enable RVV
,
liweiwei
,
23:41
Re: [PATCH for-8.1 v3 25/26] target/riscv: allow write_misa() to enable RVG
,
liweiwei
,
23:25
Re: [PATCH for-8.1 v3 15/26] target/riscv/cpu.c: split RVG code from validate_set_extensions()
,
liweiwei
,
23:10
Re: [PATCH for-8.1 v3 04/26] target/riscv: add PRIV_VERSION_LATEST
,
LIU Zhiwei
,
21:51
Re: [PATCH for-8.1 v3 03/26] target/riscv/cpu.c: remove set_priv_version()
,
LIU Zhiwei
,
21:50
Re: [PATCH for-8.1 v3 02/26] target/riscv/cpu.c: remove set_vext_version()
,
LIU Zhiwei
,
21:49
Re: [PATCH for-8.1 v3 01/26] target/riscv/cpu.c: add riscv_cpu_validate_v()
,
LIU Zhiwei
,
21:48
March 18, 2023
[PATCH for-8.1 v3 26/26] target/riscv: allow write_misa() to enable RVV
,
Daniel Henrique Barboza
,
16:06
[PATCH for-8.1 v3 25/26] target/riscv: allow write_misa() to enable RVG
,
Daniel Henrique Barboza
,
16:05
[PATCH for-8.1 v3 24/26] target/riscv: update cpu->cfg misa bits in commit_cpu_cfg()
,
Daniel Henrique Barboza
,
16:05
[PATCH for-8.1 v3 23/26] target/riscv: rework write_misa()
,
Daniel Henrique Barboza
,
16:05
[PATCH for-8.1 v3 22/26] target/riscv: use misa_ext val in riscv_cpu_validate_extensions()
,
Daniel Henrique Barboza
,
16:05
[PATCH for-8.1 v3 21/26] target/riscv: split riscv_cpu_validate_set_extensions()
,
Daniel Henrique Barboza
,
16:05
[PATCH for-8.1 v3 20/26] target/riscv: make validate_misa_ext() use a misa_ext val
,
Daniel Henrique Barboza
,
16:05
[PATCH for-8.1 v3 19/26] target/riscv: write env->misa_ext* in register_generic_cpu_props()
,
Daniel Henrique Barboza
,
16:05
[PATCH for-8.1 v3 18/26] target/riscv: error out on priv failure for RVH
,
Daniel Henrique Barboza
,
16:05
[PATCH for-8.1 v3 17/26] target/riscv: move riscv_cpu_validate_v() to validate_misa_ext()
,
Daniel Henrique Barboza
,
16:05
[PATCH for-8.1 v3 16/26] target/riscv/cpu.c: add riscv_cpu_validate_misa_ext()
,
Daniel Henrique Barboza
,
16:05
[PATCH for-8.1 v3 15/26] target/riscv/cpu.c: split RVG code from validate_set_extensions()
,
Daniel Henrique Barboza
,
16:05
[PATCH for-8.1 v3 14/26] target/riscv: add RVG
,
Daniel Henrique Barboza
,
16:05
[PATCH for-8.1 v3 13/26] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers
,
Daniel Henrique Barboza
,
16:05
[PATCH for-8.1 v3 12/26] target/riscv/cpu.c: redesign register_cpu_props()
,
Daniel Henrique Barboza
,
16:05
[PATCH for-8.1 v3 11/26] target/riscv/cpu.c: set cpu config in set_misa()
,
Daniel Henrique Barboza
,
16:05
[PATCH for-8.1 v3 10/26] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions()
,
Daniel Henrique Barboza
,
16:05
[PATCH for-8.1 v3 09/26] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
,
Daniel Henrique Barboza
,
16:05
[PATCH for-8.1 v3 08/26] target/riscv/cpu.c: validate extensions before riscv_timer_init()
,
Daniel Henrique Barboza
,
16:05
[PATCH for-8.1 v3 07/26] target/riscv: move pmp and epmp validations to validate_set_extensions()
,
Daniel Henrique Barboza
,
16:05
[PATCH for-8.1 v3 06/26] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
,
Daniel Henrique Barboza
,
16:05
[PATCH for-8.1 v3 05/26] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers
,
Daniel Henrique Barboza
,
16:05
[PATCH for-8.1 v3 04/26] target/riscv: add PRIV_VERSION_LATEST
,
Daniel Henrique Barboza
,
16:04
[PATCH for-8.1 v3 03/26] target/riscv/cpu.c: remove set_priv_version()
,
Daniel Henrique Barboza
,
16:04
[PATCH for-8.1 v3 02/26] target/riscv/cpu.c: remove set_vext_version()
,
Daniel Henrique Barboza
,
16:04
[PATCH for-8.1 v3 01/26] target/riscv/cpu.c: add riscv_cpu_validate_v()
,
Daniel Henrique Barboza
,
16:04
[PATCH for-8.1 v3 00/26] target/riscv: rework CPU extensions validation
,
Daniel Henrique Barboza
,
16:04
March 17, 2023
Re: [PATCH v2 28/32] contrib/gitdm: add Amazon to the domain map
,
Alexander Graf
,
09:18
Re: [PATCH v2 06/32] include/qemu: add documentation for memory callbacks
,
Thomas Huth
,
08:11
Re: [PATCH v2 07/32] tests/tcg: add some help output for running individual tests
,
Thomas Huth
,
08:08
Re: [PATCH v2 02/32] tests/docker: all add DOCKER_BUILDKIT to RUNC environment
,
Thomas Huth
,
08:05
Re: [PATCH for-8.1 v2 25/26] target/riscv: rework write_misa()
,
Daniel Henrique Barboza
,
07:54
Re: [PATCH v4] target/riscv: fix H extension TVM trap
,
LIU Zhiwei
,
04:45
Re: [PATCH qemu v2] linux-user: Emulate /proc/cpuinfo output for riscv
,
LIU Zhiwei
,
03:33
Re: [PATCH v2 31/32] contrib/gitdm: add more individual contributors
,
Thomas Huth
,
03:26
Re: [PATCH v2 05/32] gitlab: update centos-8-stream job
,
Thomas Huth
,
03:24
Re: [PATCH v3 1/3] numa: Validate cluster and NUMA node boundary if required
,
Gavin Shan
,
02:29
[PATCH v4 3/3] hw/riscv: Validate cluster and NUMA node boundary
,
Gavin Shan
,
02:27
[PATCH v4 2/3] hw/arm: Validate cluster and NUMA node boundary
,
Gavin Shan
,
02:27
[PATCH v4 1/3] numa: Validate cluster and NUMA node boundary if required
,
Gavin Shan
,
02:27
[PATCH v4 0/3] NUMA: Apply cluster-NUMA-node boundary for aarch64 and riscv machines
,
Gavin Shan
,
02:27
March 16, 2023
Re: [PATCH for-8.1 v2 25/26] target/riscv: rework write_misa()
,
liweiwei
,
23:04
Re: [PATCH v2 09/32] include/exec: fix kerneldoc definition
,
Peter Maydell
,
12:51
March 15, 2023
Re: [PATCH] disas/riscv: Add support for XThead* instructions
,
LIU Zhiwei
,
21:30
Re: [PATCH v2 30/32] contrib/gitdm: add revng to domain map
,
Alessandro Di Federico
,
18:57
Re: [PATCH for-8.1 v2 25/26] target/riscv: rework write_misa()
,
Daniel Henrique Barboza
,
16:38
RE: [PATCH v2 28/32] contrib/gitdm: add Amazon to the domain map
,
Durrant, Paul
,
15:55
[PATCH v2 11/32] tcg: Clear plugin_mem_cbs on TB exit
,
Alex Bennée
,
13:59
[PATCH v2 22/32] iotests: connect stdin to /dev/null when running tests
,
Alex Bennée
,
13:59
[PATCH v2 25/32] iotests: remove the check-block.sh script
,
Alex Bennée
,
13:59
[PATCH v2 13/32] include/qemu/plugin: Remove QEMU_PLUGIN_ASSERT
,
Alex Bennée
,
13:50
[PATCH v2 08/32] tests/tcg: disable pauth for aarch64 gdb tests
,
Alex Bennée
,
13:50
[PATCH v2 28/32] contrib/gitdm: add Amazon to the domain map
,
Alex Bennée
,
13:50
[PATCH v2 23/32] iotests: always use a unique sub-directory per test
,
Alex Bennée
,
13:50
[PATCH v2 29/32] contrib/gitdm: add Alibaba to the domain-map
,
Alex Bennée
,
13:50
[PATCH v2 09/32] include/exec: fix kerneldoc definition
,
Alex Bennée
,
13:49
[PATCH v2 10/32] tests/avocado: don't use tags to define drive
,
Alex Bennée
,
13:49
[PATCH v2 30/32] contrib/gitdm: add revng to domain map
,
Alex Bennée
,
13:49
[PATCH v2 31/32] contrib/gitdm: add more individual contributors
,
Alex Bennée
,
13:49
[PATCH v2 12/32] tcg: Drop plugin_gen_disable_mem_helpers from tcg_gen_exit_tb
,
Alex Bennée
,
13:49
[PATCH v2 32/32] contrib/gitdm: add group map for AMD
,
Alex Bennée
,
13:44
[PATCH v2 27/32] contrib/gitdm: Add SYRMIA to the domain map
,
Alex Bennée
,
13:44
[PATCH v2 26/32] contrib/gitdm: Add ASPEED Technology to the domain map
,
Alex Bennée
,
13:44
[PATCH v2 21/32] iotests: print TAP protocol version when reporting tests
,
Alex Bennée
,
13:44
[PATCH v2 24/32] iotests: register each I/O test separately with meson
,
Alex Bennée
,
13:44
[PATCH v2 18/32] iotests: explicitly pass source/build dir to 'check' command
,
Alex Bennée
,
13:44
[PATCH v2 20/32] iotests: strip subdir path when listing tests
,
Alex Bennée
,
13:44
[PATCH v2 19/32] iotests: allow test discovery before building
,
Alex Bennée
,
13:44
[PATCH v2 17/32] include/qemu/plugin: Inline qemu_plugin_disable_mem_helpers
,
Alex Bennée
,
13:44
[PATCH v2 16/32] include/qemu: Split out plugin-event.h
,
Alex Bennée
,
13:44
[PATCH v2 15/32] *: Add missing includes of qemu/plugin.h
,
Alex Bennée
,
13:44
[PATCH v2 14/32] *: Add missing includes of qemu/error-report.h
,
Alex Bennée
,
13:43
[PATCH v2 07/32] tests/tcg: add some help output for running individual tests
,
Alex Bennée
,
13:43
[PATCH v2 06/32] include/qemu: add documentation for memory callbacks
,
Alex Bennée
,
13:43
[PATCH v2 05/32] gitlab: update centos-8-stream job
,
Alex Bennée
,
13:43
[PATCH v2 03/32] scripts/ci: add libslirp-devel to build-environment
,
Alex Bennée
,
13:43
[PATCH v2 04/32] scripts/ci: update gitlab-runner playbook to handle CentOS
,
Alex Bennée
,
13:43
[PATCH v2 02/32] tests/docker: all add DOCKER_BUILDKIT to RUNC environment
,
Alex Bennée
,
13:43
[PATCH v2 00/32] tweaks and fixes for 8.0-rc1 (tests, plugins, docs)
,
Alex Bennée
,
13:43
[PATCH v2 01/32] tests/avocado: update AArch64 tests to Alpine 3.17.2
,
Alex Bennée
,
13:43
Re: [PATCH for-8.1 v2 16/26] target/riscv/cpu.c: split RVG code from validate_set_extensions()
,
Daniel Henrique Barboza
,
09:51
[PATCH] disas/riscv: Add support for XThead* instructions
,
Christoph Muellner
,
09:35
Re: [PATCH for-8.1 v2 25/26] target/riscv: rework write_misa()
,
liweiwei
,
01:25
Re: [PATCH for-8.1 v2 22/26] target/riscv: error out on priv failure for RVH
,
liweiwei
,
01:08
Re: [PATCH 0/4] target/riscv: Some CPURISCVState related cleanup and simplification
,
Alistair Francis
,
00:57
Re: [PATCH for-8.1 v2 19/26] target/riscv/cpu:c add misa_ext V-> D & F dependency
,
liweiwei
,
00:51
Re: [PATCH for-8.1 v2 16/26] target/riscv/cpu.c: split RVG code from validate_set_extensions()
,
liweiwei
,
00:44
March 14, 2023
Re: [PATCH for-8.1 v2 15/26] target/riscv: do not allow RVG in write_misa()
,
liweiwei
,
23:52
Re: [PATCH for-8.1 v2 04/26] target/riscv: add PRIV_VERSION_LATEST
,
Richard Henderson
,
13:36
[PATCH for-8.1 v2 26/26] target/riscv: update cpu->cfg misa bits in commit_cpu_cfg()
,
Daniel Henrique Barboza
,
12:51
[PATCH for-8.1 v2 24/26] target/riscv: use misa_ext val in riscv_cpu_validate_extensions()
,
Daniel Henrique Barboza
,
12:51
[PATCH for-8.1 v2 22/26] target/riscv: error out on priv failure for RVH
,
Daniel Henrique Barboza
,
12:51
[PATCH for-8.1 v2 23/26] target/riscv: split riscv_cpu_validate_set_extensions()
,
Daniel Henrique Barboza
,
12:51
[PATCH for-8.1 v2 25/26] target/riscv: rework write_misa()
,
Daniel Henrique Barboza
,
12:51
[PATCH for-8.1 v2 21/26] target/riscv: validate_misa_ext() now validates a misa_ext val
,
Daniel Henrique Barboza
,
12:51
[PATCH for-8.1 v2 20/26] target/riscv: move riscv_cpu_validate_v() to validate_misa_ext()
,
Daniel Henrique Barboza
,
12:51
[PATCH for-8.1 v2 19/26] target/riscv/cpu:c add misa_ext V-> D & F dependency
,
Daniel Henrique Barboza
,
12:50
[PATCH for-8.1 v2 18/26] target/risc/cpu.c: add riscv_cpu_validate_misa_ext()
,
Daniel Henrique Barboza
,
12:50
[PATCH for-8.1 v2 17/26] target/riscv: write env->misa_ext* in register_generic_cpu_props()
,
Daniel Henrique Barboza
,
12:50
[PATCH for-8.1 v2 16/26] target/riscv/cpu.c: split RVG code from validate_set_extensions()
,
Daniel Henrique Barboza
,
12:50
[PATCH for-8.1 v2 15/26] target/riscv: do not allow RVG in write_misa()
,
Daniel Henrique Barboza
,
12:50
[PATCH for-8.1 v2 14/26] target/riscv: add RVG
,
Daniel Henrique Barboza
,
12:50
[PATCH for-8.1 v2 13/26] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers
,
Daniel Henrique Barboza
,
12:50
[PATCH for-8.1 v2 12/26] target/riscv/cpu.c: redesign register_cpu_props()
,
Daniel Henrique Barboza
,
12:50
[PATCH for-8.1 v2 11/26] target/riscv/cpu.c: set cpu config in set_misa()
,
Daniel Henrique Barboza
,
12:50
[PATCH for-8.1 v2 10/26] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions()
,
Daniel Henrique Barboza
,
12:50
[PATCH for-8.1 v2 09/26] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
,
Daniel Henrique Barboza
,
12:50
[PATCH for-8.1 v2 08/26] target/riscv/cpu.c: validate extensions before riscv_timer_init()
,
Daniel Henrique Barboza
,
12:50
[PATCH for-8.1 v2 07/26] target/riscv: move pmp and epmp validations to validate_set_extensions()
,
Daniel Henrique Barboza
,
12:50
[PATCH for-8.1 v2 06/26] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
,
Daniel Henrique Barboza
,
12:50
[PATCH for-8.1 v2 05/26] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers
,
Daniel Henrique Barboza
,
12:50
[PATCH for-8.1 v2 04/26] target/riscv: add PRIV_VERSION_LATEST
,
Daniel Henrique Barboza
,
12:50
[PATCH for-8.1 v2 03/26] target/riscv/cpu.c: remove set_priv_version()
,
Daniel Henrique Barboza
,
12:50
[PATCH for-8.1 v2 02/26] target/riscv/cpu.c: remove set_vext_version()
,
Daniel Henrique Barboza
,
12:50
[PATCH for-8.1 v2 01/26] target/riscv/cpu.c: add riscv_cpu_validate_v()
,
Daniel Henrique Barboza
,
12:50
[PATCH for-8.1 v2 00/26] target/riscv: rework CPU extensions validation
,
Daniel Henrique Barboza
,
12:49
Re: [PATCH v3 1/3] numa: Validate cluster and NUMA node boundary if required
,
Gavin Shan
,
02:24
Re: [PATCH 4/4] target/riscv: Simplify arguments for riscv_csrrw_check
,
Philippe Mathieu-Daudé
,
01:54
Re: [PATCH 2/4] target/riscv: Simplify getting RISCVCPU pointer from env
,
Philippe Mathieu-Daudé
,
01:52
Re: [PATCH 4/4] target/riscv: Simplify arguments for riscv_csrrw_check
,
Alistair Francis
,
01:30
Re: [PATCH 3/4] target/riscv: Simplify type conversion for CPURISCVState
,
Alistair Francis
,
01:29
Re: [PATCH 2/4] target/riscv: Simplify getting RISCVCPU pointer from env
,
Alistair Francis
,
01:25
Re: [PATCH 1/4] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
,
Alistair Francis
,
01:23
Re: [PATCH qemu v2] linux-user: Emulate /proc/cpuinfo output for riscv
,
Alistair Francis
,
00:07
March 13, 2023
Re: [PATCH qemu v2] linux-user: Emulate /proc/cpuinfo output for riscv
,
Bin Meng
,
20:54
Re: [PATCH v3 1/1] hw/riscv: Fix max size limit when put initrd to RAM
,
Daniel Henrique Barboza
,
17:32
[PATCH qemu v2] linux-user: Emulate /proc/cpuinfo output for riscv
,
~abordado
,
16:28
Re: [PATCH v3 1/1] hw/riscv: Fix max size limit when put initrd to RAM
,
Anup Patel
,
11:50
Re: [PATCH v3 1/1] hw/riscv: Fix max size limit when put initrd to RAM
,
Daniel Henrique Barboza
,
08:29
Re: [PATCH v3 1/3] numa: Validate cluster and NUMA node boundary if required
,
Philippe Mathieu-Daudé
,
07:40
Re: [PATCH v3 0/3] NUMA: Apply cluster-NUMA-node boundary for aarch64 and riscv machines
,
Gavin Shan
,
03:16
March 12, 2023
[PATCH v3 1/1] hw/riscv: Fix max size limit when put initrd to RAM
,
Hang Xu
,
22:18
[PATCH v3 0/1] Fix max initrd size limit when put initrd to RAM
,
Hang Xu
,
22:18
Re: [PATCH v2] hw/riscv: Fix the bug of max size limit when put initrd to RAM
,
Daniel Henrique Barboza
,
18:25
[PATCH v4] target/riscv: fix H extension TVM trap
,
Yi Chen
,
08:07
[PATCH v2] hw/riscv: Fix the bug of max size limit when put initrd to RAM
,
Hang Xu
,
05:40
Re: [PATCH v3] target/riscv: fix H extension TVM trap
,
liweiwei
,
05:29
March 10, 2023
[PATCH v3] target/riscv: fix H extension TVM trap
,
Yi Chen
,
11:43
Re: [PATCH v2] target/riscv: fix H extension TVM trap
,
liweiwei
,
10:28
[PATCH v2] target/riscv: fix H extension TVM trap
,
chenyi2000
,
09:36
Re: Re: [PATCH] target/riscv/csr.c: fix H extension TVM trap
,
CHEN Yi
,
05:34
Re: [PATCH] target/riscv/csr.c: fix H extension TVM trap
,
LIU Zhiwei
,
04:19
Re: Re: [PATCH] target/riscv/csr.c: fix H extension TVM trap
,
CHEN Yi
,
04:08
Re: [PATCH] Fix slli_uw decoding
,
Alistair Francis
,
00:18
March 09, 2023
Re: [PATCH] Fix slli_uw decoding
,
Alistair Francis
,
23:18
Re: [PATCH 2/2] target/riscv: Make the "virt" register writable by GDB
,
Alistair Francis
,
22:59
Re: [PATCH] target/riscv/csr.c: fix H extension TVM trap
,
LIU Zhiwei
,
21:12
Re: [PATCH for-8.1 03/17] target/riscv/cpu.c: remove set_priv_version()
,
Alistair Francis
,
19:18
Re: [PATCH 1/2] target/riscv: Expose "virt" register for GDB for reads
,
Alistair Francis
,
19:05
Re: [PATCH for-8.1 00/17] centralize CPU extensions logic
,
Daniel Henrique Barboza
,
16:15
Re: [PATCH 4/4] target/riscv: Simplify arguments for riscv_csrrw_check
,
Daniel Henrique Barboza
,
15:57
Re: [PATCH 3/4] target/riscv: Simplify type conversion for CPURISCVState
,
Daniel Henrique Barboza
,
15:56
Re: [PATCH 2/4] target/riscv: Simplify getting RISCVCPU pointer from env
,
Daniel Henrique Barboza
,
15:55
Re: [PATCH 1/4] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
,
Daniel Henrique Barboza
,
15:52
Re: [PATCH for-8.1 17/17] target/riscv: rework write_misa()
,
Daniel Henrique Barboza
,
11:35
Re: [PATCH for-8.1 17/17] target/riscv: rework write_misa()
,
Daniel Henrique Barboza
,
11:34
Re: [PATCH for-8.1 14/17] target/riscv/cpu.c: do not allow RVE to be set
,
Daniel Henrique Barboza
,
11:24
Re: [PATCH for-8.1 03/17] target/riscv/cpu.c: remove set_priv_version()
,
Daniel Henrique Barboza
,
11:22
Re: [PATCH for-8.1 04/17] target/riscv: add PRIV_VERSION_LATEST macro
,
Daniel Henrique Barboza
,
11:03
Re: [PATCH] target/riscv/csr.c: fix H extension TVM trap
,
liweiwei
,
10:28
Re: [PATCH v7 03/10] target/riscv: allow MISA writes as experimental
,
Daniel Henrique Barboza
,
10:26
Re: Re: [PATCH] target/riscv/csr.c: fix H extension TVM trap
,
CHEN Yi
,
10:02
Re: Re: [PATCH] target/riscv/csr.c: fix H extension TVM trap
,
CHEN Yi
,
09:42
[PATCH v2] target/riscv: Add RVV registers to log
,
Ivan Klokov
,
09:01
Re: [PATCH] target/riscv/csr.c: fix H extension TVM trap
,
liweiwei
,
02:48
Re: [PATCH for-8.1 17/17] target/riscv: rework write_misa()
,
LIU Zhiwei
,
02:40
Re: [PATCH for-8.1 04/17] target/riscv: add PRIV_VERSION_LATEST macro
,
LIU Zhiwei
,
02:31
Re: [PATCH for-8.1 03/17] target/riscv/cpu.c: remove set_priv_version()
,
LIU Zhiwei
,
02:29
Re: [PATCH for-8.1 02/17] target/riscv/cpu.c: remove set_vext_version()
,
LIU Zhiwei
,
02:28
Re: [PATCH for-8.1 17/17] target/riscv: rework write_misa()
,
LIU Zhiwei
,
02:27
[PATCH 3/4] target/riscv: Simplify type conversion for CPURISCVState
,
Weiwei Li
,
02:13
[PATCH 0/4] target/riscv: Some CPURISCVState related cleanup and simplification
,
Weiwei Li
,
02:13
[PATCH 1/4] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
,
Weiwei Li
,
02:13
[PATCH 4/4] target/riscv: Simplify arguments for riscv_csrrw_check
,
Weiwei Li
,
02:13
[PATCH 2/4] target/riscv: Simplify getting RISCVCPU pointer from env
,
Weiwei Li
,
02:13
Re: [PATCH for-8.1 14/17] target/riscv/cpu.c: do not allow RVE to be set
,
LIU Zhiwei
,
02:11
Re: [PATCH v7 03/10] target/riscv: allow MISA writes as experimental
,
LIU Zhiwei
,
01:11
March 08, 2023
Re: [PATCH 2/2] target/riscv: Make the "virt" register writable by GDB
,
LIU Zhiwei
,
22:21
Re: [PATCH 2/2] target/riscv: Make the "virt" register writable by GDB
,
Jim Shu
,
22:05
Re: [PATCH for-8.1 05/17] target/riscv/cpu.c: add riscv_cpu_validate_priv_spec()
,
Richard Henderson
,
18:06
Re: [PATCH for-8.1 04/17] target/riscv: add PRIV_VERSION_LATEST macro
,
Richard Henderson
,
18:00
[PATCH for-8.1 17/17] target/riscv: rework write_misa()
,
Daniel Henrique Barboza
,
15:20
[PATCH for-8.1 16/17] target/riscv: do not allow RVG in write_misa()
,
Daniel Henrique Barboza
,
15:20
[PATCH for-8.1 15/17] target/riscv: add RVG
,
Daniel Henrique Barboza
,
15:20
[PATCH for-8.1 14/17] target/riscv/cpu.c: do not allow RVE to be set
,
Daniel Henrique Barboza
,
15:20
[PATCH for-8.1 13/17] target/riscv/cpu.c: split riscv_cpu_validate_priv_spec()
,
Daniel Henrique Barboza
,
15:20
[PATCH for-8.1 12/17] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers
,
Daniel Henrique Barboza
,
15:20
[PATCH for-8.1 11/17] target/riscv/cpu.c: move riscv_cpu_validate_v() up
,
Daniel Henrique Barboza
,
15:20
[PATCH for-8.1 10/17] target/riscv/cpu.c: redesign register_cpu_props()
,
Daniel Henrique Barboza
,
15:20
[PATCH for-8.1 09/17] target/riscv/cpu.c: set cpu config in set_misa()
,
Daniel Henrique Barboza
,
15:20
[PATCH for-8.1 08/17] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions()
,
Daniel Henrique Barboza
,
15:20
[PATCH for-8.1 07/17] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
,
Daniel Henrique Barboza
,
15:19
[PATCH for-8.1 06/17] target/riscv: move realize() validations to riscv_cpu_validate_set_extensions()
,
Daniel Henrique Barboza
,
15:19
[PATCH for-8.1 05/17] target/riscv/cpu.c: add riscv_cpu_validate_priv_spec()
,
Daniel Henrique Barboza
,
15:19
[PATCH for-8.1 04/17] target/riscv: add PRIV_VERSION_LATEST macro
,
Daniel Henrique Barboza
,
15:19
[PATCH for-8.1 03/17] target/riscv/cpu.c: remove set_priv_version()
,
Daniel Henrique Barboza
,
15:19
[PATCH for-8.1 02/17] target/riscv/cpu.c: remove set_vext_version()
,
Daniel Henrique Barboza
,
15:19
[PATCH for-8.1 01/17] target/riscv/cpu.c: add riscv_cpu_validate_v()
,
Daniel Henrique Barboza
,
15:19
[PATCH for-8.1 00/17] centralize CPU extensions logic
,
Daniel Henrique Barboza
,
15:19
Re: [PATCH] target/riscv/csr.c: fix H extension TVM trap
,
Daniel Henrique Barboza
,
14:44
[PATCH 10/47] hw/nvme: fix missing cq eventidx update
,
Michael Tokarev
,
12:37
[PATCH] target/riscv/csr.c: fix H extension TVM trap
,
chenyi2000
,
09:17
Re: [PATCH 2/2] target/riscv: Make the "virt" register writable by GDB
,
Jim Shu
,
06:15
March 07, 2023
[PULL 20/30] gdbstub: move register helpers into standalone include
,
Alex Bennée
,
16:29
[PULL 07/30] includes: move tb_flush into its own header
,
Alex Bennée
,
16:21
Re: [PULL 00/22] Sixth RISC-V PR for 8.0
,
Peter Maydell
,
09:33
Re: [PATCH 56/70] target/tricore: Split t_n as constant from temp as variable
,
Philippe Mathieu-Daudé
,
05:20
[PATCH v12 09/10] disas/riscv.c: add disasm support for Zc*
,
Weiwei Li
,
03:22
[PATCH v12 10/10] target/riscv: Add support for Zce
,
Weiwei Li
,
03:14
[PATCH v12 07/10] target/riscv: add support for Zcmt extension
,
Weiwei Li
,
03:14
[PATCH v12 02/10] target/riscv: add support for Zca extension
,
Weiwei Li
,
03:14
[PATCH v12 06/10] target/riscv: add support for Zcmp extension
,
Weiwei Li
,
03:14
[PATCH v12 04/10] target/riscv: add support for Zcd extension
,
Weiwei Li
,
03:14
[PATCH v12 08/10] target/riscv: expose properties for Zc* extension
,
Weiwei Li
,
03:14
[PATCH v12 01/10] target/riscv: add cfg properties for Zc* extension
,
Weiwei Li
,
03:14
[PATCH v12 00/10] support subsets of code size reduction extension
,
Weiwei Li
,
03:14
[PATCH v12 03/10] target/riscv: add support for Zcf extension
,
Weiwei Li
,
03:14
[PATCH v12 05/10] target/riscv: add support for Zcb extension
,
Weiwei Li
,
03:14
Re: [PATCH] Fix slli_uw decoding
,
Ivan Klokov
,
02:31
March 06, 2023
[PATCH v3 0/1] hw/riscv: Add ACT related support
,
Weiwei Li
,
22:29
[PATCH v3 1/1] hw/riscv: Add signature dump function for spike to run ACT tests
,
Weiwei Li
,
22:29
Re: [PATCH qemu] linux-user: Emulate /proc/cpuinfo output for riscv
,
LIU Zhiwei
,
21:34
Re: [PATCH 56/70] target/tricore: Split t_n as constant from temp as variable
,
Richard Henderson
,
21:24
Re: [PATCH 1/1] hw/riscv: Add signature dump function for spike to run ACT tests
,
LIU Zhiwei
,
20:47
Re: [PATCH 23/70] target/i386: Avoid use of tcg_const_* throughout
,
Philippe Mathieu-Daudé
,
19:37
Re: [PATCH 47/70] target/rx: Use cpu_psw_z as temp in flags computation
,
Philippe Mathieu-Daudé
,
19:32
Re: [PATCH 14/70] target/cris: Avoid use of tcg_const_i32 throughout
,
Philippe Mathieu-Daudé
,
19:30
Re: [PATCH 49/70] target/rx: Avoid tcg_const_i32
,
Philippe Mathieu-Daudé
,
19:27
Re: [PATCH 63/70] target/xtensa: Tidy translate_clamps
,
Philippe Mathieu-Daudé
,
19:24
Re: [PATCH 52/70] target/sh4: Avoid tcg_const_i32 for TAS.B
,
Philippe Mathieu-Daudé
,
19:23
Re: [PATCH 51/70] target/s390x: Avoid tcg_const_i64
,
Philippe Mathieu-Daudé
,
19:21
Re: [PATCH 53/70] target/sh4: Avoid tcg_const_i32
,
Philippe Mathieu-Daudé
,
19:21
Re: [PATCH 56/70] target/tricore: Split t_n as constant from temp as variable
,
Philippe Mathieu-Daudé
,
19:19
Re: [PATCH 61/70] target/tricore: Avoid tcg_const_i32
,
Philippe Mathieu-Daudé
,
19:10
Re: [PATCH 62/70] target/xtensa: Tidy translate_bb
,
Philippe Mathieu-Daudé
,
19:08
Re: [PATCH 67/70] target/xtensa: Avoid tcg_const_i32
,
Philippe Mathieu-Daudé
,
19:06
Re: [PATCH 27/70] target/m68k: Avoid tcg_const_i32 in bfop_reg
,
Philippe Mathieu-Daudé
,
19:04
Re: [PATCH 28/70] target/m68k: Avoid tcg_const_* throughout
,
Philippe Mathieu-Daudé
,
18:59
Re: [PATCH 26/70] target/m68k: Avoid tcg_const_i32 when modified
,
Philippe Mathieu-Daudé
,
18:54
Re: [PATCH 21/70] target/hppa: Avoid use of tcg_const_i32 throughout
,
Philippe Mathieu-Daudé
,
18:52
Re: [PATCH 13/70] target/avr: Avoid use of tcg_const_i32 throughout
,
Philippe Mathieu-Daudé
,
18:49
[PULL 20/22] hw/riscv/virt: virt-acpi-build.c: Add RHCT Table
,
Palmer Dabbelt
,
17:05
[PULL 21/22] hw/riscv/virt.c: Initialize the ACPI tables
,
Palmer Dabbelt
,
17:05
[PULL 22/22] MAINTAINERS: Add entry for RISC-V ACPI
,
Palmer Dabbelt
,
17:05
[PULL 18/22] hw/riscv/virt: Enable basic ACPI infrastructure
,
Palmer Dabbelt
,
17:04
[PULL 19/22] hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT
,
Palmer Dabbelt
,
17:04
[PULL 16/22] hw/riscv/virt: Add a switch to disable ACPI
,
Palmer Dabbelt
,
17:04
[PULL 15/22] hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fields
,
Palmer Dabbelt
,
17:04
[PULL 17/22] hw/riscv/virt: Add memmap pointer to RiscVVirtState
,
Palmer Dabbelt
,
17:04
[PULL 09/22] roms/opensbi: Upgrade from v1.1 to v1.2
,
Palmer Dabbelt
,
17:04
[PULL 13/22] riscv: Introduce satp mode hw capabilities
,
Palmer Dabbelt
,
17:04
[PULL 14/22] riscv: Correctly set the device-tree entry 'mmu-type'
,
Palmer Dabbelt
,
17:04
[PULL 12/22] riscv: Allow user to set the satp mode
,
Palmer Dabbelt
,
17:04
[PULL 10/22] riscv: Pass Object to register_cpu_props instead of DeviceState
,
Palmer Dabbelt
,
17:04
[PULL 11/22] riscv: Change type of valid_vm_1_10_[32|64] to bool
,
Palmer Dabbelt
,
17:04
[PULL 07/22] hw: intc: Use cpu_by_arch_id to fetch CPU state
,
Palmer Dabbelt
,
17:04
[PULL 08/22] gitlab/opensbi: Move to docker:stable
,
Palmer Dabbelt
,
17:04
[PULL 06/22] target/riscv: cpu: Implement get_arch_id callback
,
Palmer Dabbelt
,
17:04
[PULL 04/22] hw/riscv/virt.c: add cbo[mz]-block-size fdt properties
,
Palmer Dabbelt
,
17:04
[PULL 03/22] target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder
,
Palmer Dabbelt
,
17:04
[PULL 05/22] disas/riscv Fix ctzw disassemble
,
Palmer Dabbelt
,
17:04
[PULL 02/22] target/riscv: implement Zicbom extension
,
Palmer Dabbelt
,
17:04
[PULL 01/22] target/riscv: implement Zicboz extension
,
Palmer Dabbelt
,
17:04
[PULL 00/22] Sixth RISC-V PR for 8.0
,
Palmer Dabbelt
,
17:04
Re: [PATCH qemu] linux-user: Emulate /proc/cpuinfo output for riscv
,
Laurent Vivier
,
16:30
[PATCH qemu] linux-user: Emulate /proc/cpuinfo output for riscv
,
~abordado
,
16:19
Re: [Qemu-devel] [PULL 11/29] target/riscv: Convert RV32F insns to decodetree
,
Richard Henderson
,
15:22
Re: [PATCH V5 0/8] Add basic ACPI support for risc-v virt
,
Palmer Dabbelt
,
14:50
Re: [PATCH v11 0/5] riscv: Allow user to set the satp mode
,
Palmer Dabbelt
,
14:07
Re: [PATCH qemu] linux-user: Emulate /proc/cpuinfo output for riscv
,
Palmer Dabbelt
,
14:05
Re: [PATCH v11 0/5] riscv: Allow user to set the satp mode
,
Daniel Henrique Barboza
,
12:51
Re: [PATCH v11 0/5] riscv: Allow user to set the satp mode
,
Palmer Dabbelt
,
11:24
Re: [PATCH 59/70] target/tricore: Use setcondi instead of explicit allocation
,
Philippe Mathieu-Daudé
,
10:39
Re: [PATCH 57/70] target/tricore: Rename t_off10 and use tcg_constant_i32
,
Philippe Mathieu-Daudé
,
10:38
Re: [PATCH 55/70] target/sparc: Avoid tcg_const_{tl,i32}
,
Philippe Mathieu-Daudé
,
10:38
Re: [PATCH 54/70] tcg/sparc: Avoid tcg_const_tl in gen_edge
,
Philippe Mathieu-Daudé
,
10:36
Re: [PATCH 68/70] tcg: Replace tcg_const_i64 in tcg-op.c
,
Philippe Mathieu-Daudé
,
10:33
Re: [PATCH 70/70] tcg: Drop tcg_const_*
,
Philippe Mathieu-Daudé
,
10:33
Re: [PATCH 69/70] tcg: Drop tcg_const_*_vec
,
Philippe Mathieu-Daudé
,
10:33
Re: [PATCH 60/70] target/tricore: Drop some temp initialization
,
Philippe Mathieu-Daudé
,
10:25
Re: [PATCH 11/70] target/arm: Avoid tcg_const_ptr in handle_rev
,
Philippe Mathieu-Daudé
,
10:22
Re: [PATCH 10/70] target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn
,
Philippe Mathieu-Daudé
,
10:15
Re: [PATCH 07/70] target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str}
,
Philippe Mathieu-Daudé
,
10:11
Re: [PATCH 34/70] target/ppc: Split out gen_vx_vmul10
,
Philippe Mathieu-Daudé
,
10:08
Re: [PATCH 64/70] target/xtensa: Avoid tcg_const_i32 in translate_l32r
,
Philippe Mathieu-Daudé
,
10:02
Re: [PATCH 65/70] target/xtensa: Use tcg_gen_subfi_i32 in translate_sll
,
Philippe Mathieu-Daudé
,
10:02
Re: [PATCH 66/70] target/xtensa: Split constant in bit shift
,
Philippe Mathieu-Daudé
,
10:01
Re: [PATCH 48/70] target/rx: Avoid tcg_const_i32 when new temp needed
,
Philippe Mathieu-Daudé
,
09:18
Re: [PATCH 35/70] target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad
,
Philippe Mathieu-Daudé
,
09:16
Re: [PATCH 25/70] target/m68k: Use tcg_constant_i32 in gen_ea_mode
,
Philippe Mathieu-Daudé
,
09:14
Re: [Qemu-devel] [PULL 11/29] target/riscv: Convert RV32F insns to decodetree
,
Philippe Mathieu-Daudé
,
09:11
Re: [PATCH 03/70] target/arm: Improve arm_rmode_to_sf
,
Philippe Mathieu-Daudé
,
09:01
Re: [PATCH 04/70] target/arm: Consistently use ARMFPRounding during translation
,
Philippe Mathieu-Daudé
,
08:59
Re: [PATCH 01/70] target/arm: Use rmode >= 0 for need_rmode
,
Philippe Mathieu-Daudé
,
08:56
Re: [PATCH 01/70] target/arm: Use rmode >= 0 for need_rmode
,
Philippe Mathieu-Daudé
,
08:54
Re: [PATCH 45/70] target/riscv: Avoid tcg_const_*
,
liweiwei
,
08:53
Re: [PATCH 12/70] target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS
,
Philippe Mathieu-Daudé
,
08:51
Re: [PATCH 20/70] target/hppa: Avoid tcg_const_i64 in trans_fid_f
,
Philippe Mathieu-Daudé
,
08:50
Re: [PATCH 46/70] target/rx: Use tcg_gen_abs_i32
,
Philippe Mathieu-Daudé
,
08:48
Re: [PATCH 33/70] target/mips: Avoid tcg_const_* throughout
,
Philippe Mathieu-Daudé
,
08:46
Re: [PATCH 32/70] target/mips: Avoid tcg_const_tl in gen_r6_ld
,
Philippe Mathieu-Daudé
,
08:41
Re: [PATCH 31/70] target/mips: Split out gen_lxr
,
Philippe Mathieu-Daudé
,
08:41
Re: [PATCH 30/70] target/mips: Split out gen_lxl
,
Philippe Mathieu-Daudé
,
08:31
[PATCH v2 1/1] hw/riscv: Add signature dump function for spike to run ACT tests
,
Weiwei Li
,
08:24
[PATCH v2 0/1] hw/riscv: Add ACT related support
,
Weiwei Li
,
08:24
Re: [PATCH 1/1] hw/riscv: Add signature dump function for spike to run ACT tests
,
liweiwei
,
07:10
Re: [PATCH 2/2] target/riscv: Make the "virt" register writable by GDB
,
LIU Zhiwei
,
06:26
Re: [PATCH 1/2] target/riscv: Expose "virt" register for GDB for reads
,
LIU Zhiwei
,
06:22
Re: [PATCH 1/1] hw/riscv: Add signature dump function for spike to run ACT tests
,
LIU Zhiwei
,
06:01
[PATCH 0/1] hw/riscv: Add ACT related support
,
Weiwei Li
,
04:04
[PATCH 1/1] hw/riscv: Add signature dump function for spike to run ACT tests
,
Weiwei Li
,
04:04
Re: [PATCH v11 0/5] riscv: Allow user to set the satp mode
,
Alexandre Ghiti
,
03:33
March 05, 2023
Re: [PATCH V5 0/8] Add basic ACPI support for risc-v virt
,
Palmer Dabbelt
,
18:45
Re: [PATCH v2 1/2] gitlab/opensbi: Move to docker:stable
,
Palmer Dabbelt
,
18:43
Re: [PATCH 0/2] Risc-V CPU state by hart ID
,
Palmer Dabbelt
,
18:41
Re: [PATCH v11 0/5] riscv: Allow user to set the satp mode
,
Palmer Dabbelt
,
18:34
Re: [PATCH] [PATCH] disas/riscv Fix ctzw disassemble
,
Palmer Dabbelt
,
15:47
Re: [PATCH 1/1] hw/riscv/virt.c: add cbom-block-size fdt property
,
Palmer Dabbelt
,
15:39
Re: [PATCH v8 0/4] riscv: Add support for Zicbo[m,z,p] instructions
,
Palmer Dabbelt
,
15:39
Re: [PATCH v2 0/1] hw/riscv/virt.c: add cbo[mz]-block-size fdt properties
,
Palmer Dabbelt
,
15:39
Re: [PATCH] hw/riscv: Fix the bug of maximum size limit when put initrd to RAM
,
Hang Xu
,
06:11
[PATCH 2/2] target/riscv: Make the "virt" register writable by GDB
,
Jim Shu
,
04:42
[PATCH 1/2] target/riscv: Expose "virt" register for GDB for reads
,
Jim Shu
,
04:42
March 03, 2023
Re: [PATCH v2 1/2] gitlab/opensbi: Move to docker:stable
,
Bin Meng
,
18:28
[PATCH v2 2/2] roms/opensbi: Upgrade from v1.1 to v1.2
,
Palmer Dabbelt
,
15:25
[PATCH v2 1/2] gitlab/opensbi: Move to docker:stable
,
Palmer Dabbelt
,
15:25
[PATCH v2 0/2] Fix the OpenSBI CI job and bump to v1.2
,
Palmer Dabbelt
,
15:25
Re: [PATCH 2/2] hw: intc: Use cpu_by_arch_id to fetch CPU state
,
Daniel Henrique Barboza
,
15:05
Re: [PATCH 1/2] target/riscv: cpu: Implement get_arch_id callback
,
Daniel Henrique Barboza
,
15:05
Re: [PATCH v2 00/76] tcg: Drop tcg_temp_free from translators
,
Peter Maydell
,
14:12
Re: [PATCH v2 66/76] target/sparc: Drop get_temp_i32
,
Peter Maydell
,
14:09
Re: [PATCH v2 69/76] target/sparc: Drop tcg_temp_free
,
Peter Maydell
,
14:08
Re: [PATCH v2 68/76] target/sparc: Drop free_compare
,
Peter Maydell
,
14:08
Re: [PATCH v2 67/76] target/sparc: Remove egress label in disas_sparc_context
,
Peter Maydell
,
14:07
Re: [PATCH 66/76] target/sparc: Drop get_temp_i32
,
Peter Maydell
,
14:06
Re: [PATCH v2 65/76] target/sparc: Drop get_temp_tl
,
Peter Maydell
,
14:05
Re: [PATCH v2 35/76] target/m68k: Drop tcg_temp_free
,
Peter Maydell
,
14:04
Re: [PATCH v2 34/76] target/m68k: Drop free_cond
,
Peter Maydell
,
13:58
Re: [PATCH v2 33/76] target/m68k: Drop mark_to_release
,
Peter Maydell
,
13:57
Re: [PATCH v2 36/76] target/microblaze: Drop tcg_temp_free
,
Peter Maydell
,
13:55
Re: [PATCH v2 29/76] target/hppa: Drop tcg_temp_free
,
Peter Maydell
,
13:54
Re: [PATCH v2 49/76] target/openrisc: Drop tcg_temp_free
,
Peter Maydell
,
13:52
Re: [PATCH v2 64/76] target/sh4: Drop tcg_temp_free
,
Peter Maydell
,
13:51
Re: [PATCH v2 54/76] target/rx: Drop tcg_temp_free
,
Peter Maydell
,
13:50
Re: [PATCH v2 48/76] target/nios2: Drop tcg_temp_free
,
Peter Maydell
,
13:49
Re: [PATCH v2 23/76] target/cris: Drop addr from dec10_ind_move_m_pr
,
Peter Maydell
,
13:49
Re: [PATCH v2 24/76] target/cris: Drop tcg_temp_free
,
Peter Maydell
,
13:47
Re: [PATCH v2 22/76] target/cris: Drop cris_alu_m_free_temps
,
Peter Maydell
,
13:47
Re: [PATCH v2 21/76] target/cris: Drop cris_alu_free_temps
,
Peter Maydell
,
13:46
Re: [PATCH v2 20/76] target/avr: Drop tcg_temp_free
,
Peter Maydell
,
13:46
Re: [PATCH v2 19/76] target/avr: Drop R from trans_COM
,
Peter Maydell
,
13:44
Re: [PATCH v2 18/76] target/avr: Drop DisasContext.free_skip_var0
,
Peter Maydell
,
13:43
Re: [PATCH v2 75/76] tcg: Create tcg/tcg-temp-internal.h
,
Peter Maydell
,
13:31
Re: [PATCH v2 73/76] include/exec/gen-icount: Drop tcg_temp_free in gen_tb_start
,
Peter Maydell
,
13:28
Re: [PATCH v2 17/76] target/arm: Drop tcg_temp_free from translator.h
,
Peter Maydell
,
13:28
Re: [PATCH v2 16/76] target/arm: Drop tcg_temp_free from translator-vfp.c
,
Peter Maydell
,
13:27
Re: [PATCH v2 15/76] target/arm: Drop tcg_temp_free from translator-sve.c
,
Peter Maydell
,
13:26
Re: [PATCH v2 14/76] target/arm: Drop tcg_temp_free from translator-sme.c
,
Peter Maydell
,
13:25
Re: [PATCH v2 13/76] target/arm: Drop tcg_temp_free from translator-neon.c
,
Peter Maydell
,
12:38
Re: [PATCH v2 12/76] target/arm: Drop tcg_temp_free from translator-mve.c
,
Peter Maydell
,
12:37
Re: [PATCH v2 11/76] target/arm: Drop tcg_temp_free from translator-m-nocp.c
,
Peter Maydell
,
12:36
Re: [PATCH v2 10/76] target/arm: Drop tcg_temp_free from translator-a64.c
,
Peter Maydell
,
12:36
Re: [PATCH v2 09/76] target/arm: Drop new_tmp_a64_zero
,
Peter Maydell
,
12:34
Re: [PATCH v2 08/76] target/arm: Drop new_tmp_a64
,
Peter Maydell
,
12:33
Re: [PATCH v2 07/76] target/arm: Drop DisasContext.tmp_a64
,
Peter Maydell
,
12:31
Re: [PATCH v2 06/76] target/arm: Drop tcg_temp_free from translator.c
,
Peter Maydell
,
12:31
Re: [PATCH v2 05/76] target/arm: Remove value_global from DisasCompare
,
Peter Maydell
,
12:29
Re: [PATCH v2 04/76] target/arm: Remove arm_free_cc, a64_free_cc
,
Peter Maydell
,
12:28
Re: [PATCH v2 03/76] target/alpha: Drop tcg_temp_free
,
Peter Maydell
,
12:27
Re: [PATCH v2 02/76] accel/tcg: Remove translator_loop_temp_check
,
Peter Maydell
,
12:26
Re: [PATCH v2 01/76] tcg: Remove tcg_check_temp_count, tcg_clear_temp_count
,
Peter Maydell
,
12:26
Re: [PULL 00/59] Fifth RISC-V PR for QEMU 8.0
,
Peter Maydell
,
08:35
[PATCH v11 5/5] riscv: Correctly set the device-tree entry 'mmu-type'
,
Alexandre Ghiti
,
08:18
[PATCH v11 4/5] riscv: Introduce satp mode hw capabilities
,
Alexandre Ghiti
,
08:17
[PATCH v11 3/5] riscv: Allow user to set the satp mode
,
Alexandre Ghiti
,
08:16
[PATCH v11 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool
,
Alexandre Ghiti
,
08:15
[PATCH v11 1/5] riscv: Pass Object to register_cpu_props instead of DeviceState
,
Alexandre Ghiti
,
08:14
[PATCH v11 0/5] riscv: Allow user to set the satp mode
,
Alexandre Ghiti
,
08:13
Re: [PULL 00/59] Fifth RISC-V PR for QEMU 8.0
,
Peter Maydell
,
07:21
Re: [PATCH v10 0/5] riscv: Allow user to set the satp mode
,
Alexandre Ghiti
,
06:52
[PULL 59/59] target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig
,
Palmer Dabbelt
,
03:42
[PULL 54/59] target/riscv/csr.c: use env_archcpu() in ctr()
,
Palmer Dabbelt
,
03:42
[PULL 56/59] target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers
,
Palmer Dabbelt
,
03:42
[PULL 58/59] target/riscv/vector_helper.c: create vext_set_tail_elems_1s()
,
Palmer Dabbelt
,
03:42
[PULL 57/59] target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig
,
Palmer Dabbelt
,
03:42
[PULL 53/59] target/riscv: Export Svadu property
,
Palmer Dabbelt
,
03:42
[PULL 52/59] target/riscv: Add *envcfg.HADE related check in address translation
,
Palmer Dabbelt
,
03:42
[PULL 51/59] target/riscv: Add *envcfg.PBMTE related check in address translation
,
Palmer Dabbelt
,
03:42
[PULL 50/59] target/riscv: Add csr support for svadu
,
Palmer Dabbelt
,
03:42
[PULL 49/59] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg
,
Palmer Dabbelt
,
03:42
[PULL 47/59] hw/riscv: Move the dtb load bits outside of create_fdt()
,
Palmer Dabbelt
,
03:42
[PULL 55/59] target/riscv/csr.c: simplify mctr()
,
Palmer Dabbelt
,
03:42
[PULL 45/59] target/riscv: Add support for Zicond extension
,
Palmer Dabbelt
,
03:42
[PULL 48/59] target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions
,
Palmer Dabbelt
,
03:42
[PULL 42/59] target/riscv: Group all predicate() routines together
,
Palmer Dabbelt
,
03:42
[PULL 41/59] target/riscv: Drop priv level check in mseccfg predicate()
,
Palmer Dabbelt
,
03:42
[PULL 40/59] target/riscv: Allow debugger to access sstc CSRs
,
Palmer Dabbelt
,
03:42
[PULL 46/59] hw/riscv: Skip re-generating DT nodes for a given DTB
,
Palmer Dabbelt
,
03:42
[PULL 37/59] target/riscv: Allow debugger to access user timer and counter CSRs
,
Palmer Dabbelt
,
03:42
[PULL 38/59] target/riscv: Allow debugger to access seed CSR
,
Palmer Dabbelt
,
03:42
[PULL 44/59] RISC-V: XTheadMemPair: Remove register restrictions for store-pair
,
Palmer Dabbelt
,
03:42
[PULL 43/59] target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages
,
Palmer Dabbelt
,
03:42
[PULL 39/59] target/riscv: Allow debugger to access {h, s}stateen CSRs
,
Palmer Dabbelt
,
03:42
[PULL 36/59] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml
,
Palmer Dabbelt
,
03:42
[PULL 35/59] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate()
,
Palmer Dabbelt
,
03:42
[PULL 30/59] target/riscv: Coding style fixes in csr.c
,
Palmer Dabbelt
,
03:42
[PULL 34/59] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64
,
Palmer Dabbelt
,
03:42
[PULL 33/59] target/riscv: Simplify getting RISCVCPU pointer from env
,
Palmer Dabbelt
,
03:42
[PULL 32/59] target/riscv: Simplify {read, write}_pmpcfg() a little bit
,
Palmer Dabbelt
,
03:42
[PULL 31/59] target/riscv: Use 'bool' type for read_only
,
Palmer Dabbelt
,
03:42
[PULL 29/59] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
,
Palmer Dabbelt
,
03:42
[PULL 28/59] target/riscv: gdbstub: Minor change for better readability
,
Palmer Dabbelt
,
03:42
[PULL 27/59] target/riscv: Use g_assert() for the predicate() NULL check
,
Palmer Dabbelt
,
03:41
[PULL 25/59] target/riscv: gdbstub: Check priv spec version before reporting CSR
,
Palmer Dabbelt
,
03:41
[PULL 26/59] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check()
,
Palmer Dabbelt
,
03:41
[PULL 24/59] target/riscv: Expose properties for Zv* extensions
,
Palmer Dabbelt
,
03:41
[PULL 23/59] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc
,
Palmer Dabbelt
,
03:41
[PULL 22/59] target/riscv: Fix check for vector load/store instructions when EEW=64
,
Palmer Dabbelt
,
03:41
[PULL 21/59] target/riscv: Add support for Zvfh/zvfhmin extensions
,
Palmer Dabbelt
,
03:41
[PULL 20/59] target/riscv: Remove redundunt check for zve32f and zve64f
,
Palmer Dabbelt
,
03:41
[PULL 17/59] target/riscv: Indent fixes in cpu.c
,
Palmer Dabbelt
,
03:41
[PULL 16/59] target/riscv: Add property check for Zvfh{min} extensions
,
Palmer Dabbelt
,
03:41
[PULL 19/59] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc
,
Palmer Dabbelt
,
03:41
[PULL 18/59] target/riscv: Simplify check for Zve32f and Zve64f
,
Palmer Dabbelt
,
03:41
[PULL 13/59] target/riscv: Simplify the check for Zfhmin and Zhinxmin
,
Palmer Dabbelt
,
03:41
[PULL 15/59] target/riscv: Fix relationship between V, Zve*, F and D
,
Palmer Dabbelt
,
03:41
[PULL 11/59] target/riscv: Fix the relationship between Zfhmin and Zfh
,
Palmer Dabbelt
,
03:41
[PULL 14/59] target/riscv: Add cfg properties for Zv* extensions
,
Palmer Dabbelt
,
03:41
[PULL 09/59] target/riscv: remove RISCV_FEATURE_MMU
,
Palmer Dabbelt
,
03:41
[PULL 10/59] target/riscv/cpu: remove CPUArchState::features and friends
,
Palmer Dabbelt
,
03:41
[PULL 06/59] target/riscv: remove RISCV_FEATURE_EPMP
,
Palmer Dabbelt
,
03:41
[PULL 03/59] target/riscv: allow MISA writes as experimental
,
Palmer Dabbelt
,
03:41
[PULL 02/59] target/riscv: do not mask unsupported QEMU extensions in write_misa()
,
Palmer Dabbelt
,
03:41
[PULL 12/59] target/riscv: Fix the relationship between Zhinxmin and Zhinx
,
Palmer Dabbelt
,
03:41
[PULL 08/59] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus()
,
Palmer Dabbelt
,
03:41
[PULL 07/59] target/riscv: remove RISCV_FEATURE_PMP
,
Palmer Dabbelt
,
03:41
[PULL 04/59] target/riscv: remove RISCV_FEATURE_DEBUG
,
Palmer Dabbelt
,
03:41
[PULL 05/59] target/riscv/cpu.c: error out if EPMP is enabled without PMP
,
Palmer Dabbelt
,
03:41
[PULL 01/59] target/riscv: introduce riscv_cpu_cfg()
,
Palmer Dabbelt
,
03:41
[PULL 00/59] Fifth RISC-V PR for QEMU 8.0
,
Palmer Dabbelt
,
03:41
Re: [PATCH v4 04/26] gdbstub: clean-up indent on gdb_exit
,
Daniel Henrique Barboza
,
03:33
[PATCH 2/2] hw: intc: Use cpu_by_arch_id to fetch CPU state
,
Mayuresh Chitale
,
01:51
[PATCH 1/2] target/riscv: cpu: Implement get_arch_id callback
,
Mayuresh Chitale
,
01:51
[PATCH 0/2] Risc-V CPU state by hart ID
,
Mayuresh Chitale
,
01:51
March 02, 2023
Re: [PATCH v10 0/5] riscv: Allow user to set the satp mode
,
Daniel Henrique Barboza
,
16:03
[PATCH v4 14/26] gdbstub: specialise handle_query_attached
,
Alex Bennée
,
14:14
[PATCH v4 21/26] gdbstub: move syscall handling to new file
,
Alex Bennée
,
14:14
[PATCH v4 25/26] gdbstub: split out softmmu/user specifics for syscall handling
,
Alex Bennée
,
14:14
[PATCH v4 20/26] gdbstub: move register helpers into standalone include
,
Alex Bennée
,
14:14
[PATCH v4 19/26] gdbstub: don't use target_ulong while handling registers
,
Alex Bennée
,
14:14
[PATCH v4 15/26] gdbstub: specialise target_memory_rw_debug
,
Alex Bennée
,
14:14
[PATCH v4 16/26] gdbstub: introduce gdb_get_max_cpus
,
Alex Bennée
,
14:14
[PATCH v4 17/26] gdbstub: specialise stub_can_reverse
,
Alex Bennée
,
14:14
[PATCH v4 22/26] gdbstub: only compile gdbstub twice for whole build
,
Alex Bennée
,
14:14
[PATCH v4 18/26] gdbstub: fix address type of gdb_set_cpu_pc
,
Alex Bennée
,
14:14
[PATCH v4 23/26] testing: probe gdb for supported architectures ahead of time
,
Alex Bennée
,
14:14
[PATCH v4 24/26] include: split target_long definition from cpu-defs
,
Alex Bennée
,
14:14
[PATCH v4 13/26] gdbstub: abstract target specific details from gdb_put_packet_binary
,
Alex Bennée
,
14:14
[PATCH v4 26/26] gdbstub: move update guest debug to accel ops
,
Alex Bennée
,
14:09
[PATCH v4 11/26] gdbstub: move chunks of user code into own files
,
Alex Bennée
,
14:09
[PATCH v4 09/26] gdbstub: make various helpers visible to the rest of the module
,
Alex Bennée
,
14:09
[PATCH v4 10/26] gdbstub: move chunk of softmmu functionality to own file
,
Alex Bennée
,
14:09
[PATCH v4 12/26] gdbstub: rationalise signal mapping in softmmu
,
Alex Bennée
,
14:09
[PATCH v4 08/26] gdbstub: move fromhex/tohex routines to internals
,
Alex Bennée
,
14:09
[PATCH v4 04/26] gdbstub: clean-up indent on gdb_exit
,
Alex Bennée
,
14:09
[PATCH v4 07/26] includes: move tb_flush into its own header
,
Alex Bennée
,
14:09
[PATCH v4 06/26] gdbstub: move GDBState to shared internals header
,
Alex Bennée
,
14:09
[PATCH v4 05/26] gdbstub: define separate user/system structures
,
Alex Bennée
,
14:09
[PATCH v4 03/26] gdbstub: Make syscall_complete/[gs]et_reg target-agnostic typedefs
,
Alex Bennée
,
14:08
[PATCH v4 02/26] gdbstub: fix-up copyright and license files
,
Alex Bennée
,
14:08
[PATCH v4 00/26] gdbstub/next: re-organise and split build
,
Alex Bennée
,
14:08
[PATCH v4 01/26] gdbstub/internals.h: clean up include guard
,
Alex Bennée
,
14:08
Re: [PATCH v10 0/5] riscv: Allow user to set the satp mode
,
Daniel Henrique Barboza
,
12:42
Re: [PATCH v8 0/4] riscv: Add support for Zicbo[m,z,p] instructions
,
Daniel Henrique Barboza
,
06:48
Re: [PATCH v2 1/1] hw/riscv/virt.c: add cbo[mz]-block-size fdt properties
,
Bin Meng
,
04:58
[PATCH v2 0/1] hw/riscv/virt.c: add cbo[mz]-block-size fdt properties
,
Daniel Henrique Barboza
,
04:14
[PATCH v2 1/1] hw/riscv/virt.c: add cbo[mz]-block-size fdt properties
,
Daniel Henrique Barboza
,
04:14
[PATCH V5 8/8] MAINTAINERS: Add entry for RISC-V ACPI
,
Sunil V L
,
04:13
[PATCH V5 6/8] hw/riscv/virt: virt-acpi-build.c: Add RHCT Table
,
Sunil V L
,
04:13
[PATCH V5 5/8] hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT
,
Sunil V L
,
04:12
[PATCH V5 7/8] hw/riscv/virt.c: Initialize the ACPI tables
,
Sunil V L
,
04:12
[PATCH V5 4/8] hw/riscv/virt: Enable basic ACPI infrastructure
,
Sunil V L
,
04:12
[PATCH V5 3/8] hw/riscv/virt: Add memmap pointer to RiscVVirtState
,
Sunil V L
,
04:12
[PATCH V5 2/8] hw/riscv/virt: Add a switch to disable ACPI
,
Sunil V L
,
04:12
[PATCH V5 1/8] hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fields
,
Sunil V L
,
04:12
[PATCH V5 0/8] Add basic ACPI support for risc-v virt
,
Sunil V L
,
04:12
Re: [PATCH 1/1] hw/riscv/virt.c: add cbom-block-size fdt property
,
Ben Dooks
,
04:09
Re: [PATCH 0/4] RISCVCPUConfig related cleanups
,
Daniel Henrique Barboza
,
03:11
Re: [PATCH v7 00/10] make write_misa a no-op and FEATURE_* cleanups
,
Daniel Henrique Barboza
,
03:04
Re: [PATCH] [PATCH] disas/riscv Fix ctzw disassemble
,
Ivan Klokov
,
02:42
March 01, 2023
Re: [PATCH v2 03/18] target/riscv: Use g_assert() for the predicate() NULL check
,
LIU Zhiwei
,
21:50
Re: [PATCH v2 02/18] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check()
,
LIU Zhiwei
,
21:50
Re: [PATCH v2 18/18] target/riscv: Group all predicate() routines together
,
LIU Zhiwei
,
21:47
Re: [PATCH v2 17/18] target/riscv: Drop priv level check in mseccfg predicate()
,
LIU Zhiwei
,
21:45
Re: [PATCH v2 16/18] target/riscv: Allow debugger to access sstc CSRs
,
LIU Zhiwei
,
21:45
Re: [PATCH v2 15/18] target/riscv: Allow debugger to access {h,s}stateen CSRs
,
LIU Zhiwei
,
21:44
Re: [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
,
LIU Zhiwei
,
21:44
Re: [PATCH 0/2] target/riscv: some vector_helper.c cleanups
,
Palmer Dabbelt
,
21:32
Re: [PATCH 0/2] Fix the OpenSBI CI job and bump to v1.2
,
Palmer Dabbelt
,
21:32
Re: [PATCH 0/4] RISCVCPUConfig related cleanups
,
Bin Meng
,
21:24
Re: [PATCH 1/2] target/riscv/vector_helper.c: create vext_set_tail_elems_1s()
,
Palmer Dabbelt
,
21:13
Re: [PATCH 0/4] RISCVCPUConfig related cleanups
,
Palmer Dabbelt
,
21:07
Re: [PATCH 0/6] target/riscv: Add support for Svadu extension
,
Palmer Dabbelt
,
20:36
Re: [PATCH 2/6] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg
,
Palmer Dabbelt
,
20:36
Re: [PATCH v2 1/2] hw/riscv: Skip re-generating DT nodes for a given DTB
,
Palmer Dabbelt
,
20:29
Re: [PATCH] target/riscv: Add support for Zicond extension
,
Palmer Dabbelt
,
20:17
Re: [PATCH] RISC-V: XTheadMemPair: Remove register restrictions for store-pair
,
Palmer Dabbelt
,
20:09
Re: [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
,
Palmer Dabbelt
,
19:58
Re: [PATCH] [PATCH] disas/riscv Fix ctzw disassemble
,
Palmer Dabbelt
,
19:32
Re: [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
,
Bin Meng
,
19:31
Re: [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
,
Palmer Dabbelt
,
18:43
Re: [PATCH v2 00/14] target/riscv: Some updates to float point related extensions
,
Palmer Dabbelt
,
18:43
Re: [PATCH v7 00/10] make write_misa a no-op and FEATURE_* cleanups
,
Palmer Dabbelt
,
18:43
[PATCH 1/1] hw/riscv/virt.c: add cbom-block-size fdt property
,
Daniel Henrique Barboza
,
16:59
[PATCH 0/1] hw/riscv/virt.c: add cbom-block-size fdt property
,
Daniel Henrique Barboza
,
16:59
Re: [PATCH v7 0/4] riscv: Add support for Zicbo[m,z,p] instructions
,
Daniel Henrique Barboza
,
16:44
Re: [PATCH v7 1/4] tcg: add 'size' param to probe_access_flags()
,
Palmer Dabbelt
,
16:35
Re: [PATCH v7 0/4] riscv: Add support for Zicbo[m,z,p] instructions
,
Palmer Dabbelt
,
16:35
Re: [PATCH 55/70] target/sparc: Avoid tcg_const_{tl,i32}
,
Mark Cave-Ayland
,
12:03
Re: [PATCH v2 00/76] tcg: Drop tcg_temp_free from translators
,
Mark Cave-Ayland
,
12:02
Re: [RFC PATCH 07/19] hw/scsi: Set QDev properties using QDev API
,
Igor Mammedov
,
09:13
Re: [RFC PATCH 05/19] hw/core/numa: Set QDev properties using QDev API
,
Igor Mammedov
,
09:09
Re: [PATCH 03/19] hw/acpi: Set QDev properties using QDev API
,
Igor Mammedov
,
09:07
Re: [RFC PATCH 12/19] hw/i386: Set QDev properties using QDev API
,
Igor Mammedov
,
09:00
Re: [PATCH 00/19] hw: Set QDev properties using QDev API (part 1/3)
,
Igor Mammedov
,
08:42
Re: [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
,
Bin Meng
,
04:55
Re: [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
,
LIU Zhiwei
,
04:52
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