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[PATCH 12/18] target/riscv: Allow debugger to access user timer and coun
From: |
Bin Meng |
Subject: |
[PATCH 12/18] target/riscv: Allow debugger to access user timer and counter CSRs |
Date: |
Tue, 14 Feb 2023 09:09:10 +0800 |
At present user timer and counter CSRs are not reported in the
CSR XML hence gdb cannot access them.
Fix it by addding a debugger check in their predicate() routine.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
---
target/riscv/csr.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 749d0ef83e..515b05348b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -131,6 +131,10 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
skip_ext_pmu_check:
+ if (env->debugger) {
+ return RISCV_EXCP_NONE;
+ }
+
if (env->priv < PRV_M && !get_field(env->mcounteren, ctr_mask)) {
return RISCV_EXCP_ILLEGAL_INST;
}
--
2.25.1
- Re: [PATCH 08/18] target/riscv: Simplify getting RISCVCPU pointer from env, (continued)
- [PATCH 09/18] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64, Bin Meng, 2023/02/13
- [PATCH 11/18] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml, Bin Meng, 2023/02/13
- Re: [PATCH 00/18] target/riscv: Various fixes to gdbstub and CSR access, Daniel Henrique Barboza, 2023/02/13
- [PATCH 12/18] target/riscv: Allow debugger to access user timer and counter CSRs,
Bin Meng <=
- [PATCH 13/18] target/riscv: Allow debugger to access seed CSR, Bin Meng, 2023/02/13
- [PATCH 14/18] target/riscv: Allow debugger to access {h, s}stateen CSRs, Bin Meng, 2023/02/13
- [PATCH 15/18] target/riscv: Allow debugger to access sstc CSRs, Bin Meng, 2023/02/13
- [PATCH 16/18] target/riscv: Drop priv level check in mseccfg predicate(), Bin Meng, 2023/02/13