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[PATCH 09/18] target/riscv: Avoid reporting odd-numbered pmpcfgX in the
From: |
Bin Meng |
Subject: |
[PATCH 09/18] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64 |
Date: |
Tue, 14 Feb 2023 02:02:05 +0800 |
At present the odd-numbered PMP configuration registers for RV64 are
reported in the CSR XML by QEMU gdbstub. However these registers do
not exist on RV64 so trying to access them from gdb results in 'E14'.
Move the pmpcfgX index check from the actual read/write routine to
the PMP CSR predicate() routine, so that non-existent pmpcfgX won't
be reported in the CSR XML for RV64.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
---
target/riscv/csr.c | 23 ++++++++---------------
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0a3f2bef6f..749d0ef83e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -412,6 +412,14 @@ static int aia_hmode32(CPURISCVState *env, int csrno)
static RISCVException pmp(CPURISCVState *env, int csrno)
{
if (riscv_feature(env, RISCV_FEATURE_PMP)) {
+ if (csrno <= CSR_PMPCFG3) {
+ uint32_t reg_index = csrno - CSR_PMPCFG0;
+
+ if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ }
+
return RISCV_EXCP_NONE;
}
@@ -3334,23 +3342,11 @@ static RISCVException write_mseccfg(CPURISCVState *env,
int csrno,
return RISCV_EXCP_NONE;
}
-static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index)
-{
- /* TODO: RV128 restriction check */
- if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
- return false;
- }
- return true;
-}
-
static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
target_ulong *val)
{
uint32_t reg_index = csrno - CSR_PMPCFG0;
- if (!check_pmp_reg_index(env, reg_index)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
*val = pmpcfg_csr_read(env, reg_index);
return RISCV_EXCP_NONE;
}
@@ -3360,9 +3356,6 @@ static RISCVException write_pmpcfg(CPURISCVState *env,
int csrno,
{
uint32_t reg_index = csrno - CSR_PMPCFG0;
- if (!check_pmp_reg_index(env, reg_index)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
pmpcfg_csr_write(env, reg_index, val);
return RISCV_EXCP_NONE;
}
--
2.25.1
- Re: [PATCH 02/18] target/riscv: Correct the priority policy of riscv_csrrw_check(), (continued)
- [PATCH 07/18] target/riscv: Simplify {read, write}_pmpcfg() a little bit, Bin Meng, 2023/02/13
- [PATCH 10/18] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate(), Bin Meng, 2023/02/13
- [PATCH 08/18] target/riscv: Simplify getting RISCVCPU pointer from env, Bin Meng, 2023/02/13
- [PATCH 09/18] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64,
Bin Meng <=
- [PATCH 11/18] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml, Bin Meng, 2023/02/13
- Re: [PATCH 00/18] target/riscv: Various fixes to gdbstub and CSR access, Daniel Henrique Barboza, 2023/02/13
- [PATCH 12/18] target/riscv: Allow debugger to access user timer and counter CSRs, Bin Meng, 2023/02/13