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[PATCH 14/18] target/riscv: Allow debugger to access {h, s}stateen CSRs
From: |
Bin Meng |
Subject: |
[PATCH 14/18] target/riscv: Allow debugger to access {h, s}stateen CSRs |
Date: |
Tue, 14 Feb 2023 11:06:24 +0800 |
At present {h,s}stateen CSRs are not reported in the CSR XML
hence gdb cannot access them.
Fix it by adjusting their predicate() routine logic so that the
static config check comes before the run-time check, as well as
addding a debugger check.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
---
target/riscv/csr.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f1075b5728..d6bcb7f275 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -337,13 +337,22 @@ static RISCVException hstateen_pred(CPURISCVState *env,
int csrno, int base)
return RISCV_EXCP_ILLEGAL_INST;
}
+ RISCVException ret = hmode(env, csrno);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
+
+ if (env->debugger) {
+ return RISCV_EXCP_NONE;
+ }
+
if (env->priv < PRV_M) {
if (!(env->mstateen[csrno - base] & SMSTATEEN_STATEEN)) {
return RISCV_EXCP_ILLEGAL_INST;
}
}
- return hmode(env, csrno);
+ return RISCV_EXCP_NONE;
}
static RISCVException hstateen(CPURISCVState *env, int csrno)
@@ -366,6 +375,15 @@ static RISCVException sstateen(CPURISCVState *env, int
csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+ RISCVException ret = smode(env, csrno);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
+
+ if (env->debugger) {
+ return RISCV_EXCP_NONE;
+ }
+
if (env->priv < PRV_M) {
if (!(env->mstateen[index] & SMSTATEEN_STATEEN)) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -378,7 +396,7 @@ static RISCVException sstateen(CPURISCVState *env, int
csrno)
}
}
- return smode(env, csrno);
+ return RISCV_EXCP_NONE;
}
/* Checks if PointerMasking registers could be accessed */
--
2.25.1
- Re: [PATCH 11/18] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml, (continued)
- Re: [PATCH 00/18] target/riscv: Various fixes to gdbstub and CSR access, Daniel Henrique Barboza, 2023/02/13
- [PATCH 12/18] target/riscv: Allow debugger to access user timer and counter CSRs, Bin Meng, 2023/02/13
- [PATCH 13/18] target/riscv: Allow debugger to access seed CSR, Bin Meng, 2023/02/13
- [PATCH 14/18] target/riscv: Allow debugger to access {h, s}stateen CSRs,
Bin Meng <=
- [PATCH 15/18] target/riscv: Allow debugger to access sstc CSRs, Bin Meng, 2023/02/13
- [PATCH 16/18] target/riscv: Drop priv level check in mseccfg predicate(), Bin Meng, 2023/02/13
- [PATCH 17/18] target/riscv: Group all predicate() routines together, Bin Meng, 2023/02/13
- [PATCH 18/18] target/riscv: Move configuration check to envcfg CSRs predicate(), Bin Meng, 2023/02/14