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Re: [RFC 57/65] target/riscv: rvv-0.9: floating-point min/max instructio
From: |
Alex Bennée |
Subject: |
Re: [RFC 57/65] target/riscv: rvv-0.9: floating-point min/max instructions |
Date: |
Fri, 10 Jul 2020 19:19:19 +0100 |
User-agent: |
mu4e 1.5.4; emacs 28.0.50 |
frank.chang@sifive.com writes:
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/vector_helper.c | 24 ++++++++++++------------
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 42a48be5fd..d617d0dfbd 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -3831,28 +3831,28 @@ GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4, clearl)
> GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8, clearq)
>
> /* Vector Floating-Point MIN/MAX Instructions */
> -RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum)
> -RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum)
> -RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum)
> +RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum_noprop)
> +RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum_noprop)
> +RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8,
> float64_minnum_noprop)
This patch breaks bisection because you don't introduce this into
softfloat until later. You should always ensure each step can build and
run - practically this means the softfloat changes should be at the
beginning of the series.
> GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2, clearh)
> GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4, clearl)
> GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8, clearq)
> -RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum)
> -RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum)
> -RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum)
> +RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum_noprop)
> +RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum_noprop)
> +RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum_noprop)
> GEN_VEXT_VF(vfmin_vf_h, 2, 2, clearh)
> GEN_VEXT_VF(vfmin_vf_w, 4, 4, clearl)
> GEN_VEXT_VF(vfmin_vf_d, 8, 8, clearq)
>
> -RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum)
> -RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum)
> -RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum)
> +RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum_noprop)
> +RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum_noprop)
> +RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum_noprop)
> GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2, clearh)
> GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4, clearl)
> GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8, clearq)
> -RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum)
> -RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum)
> -RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum)
> +RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum_noprop)
> +RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum_noprop)
> +RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum_noprop)
> GEN_VEXT_VF(vfmax_vf_h, 2, 2, clearh)
> GEN_VEXT_VF(vfmax_vf_w, 4, 4, clearl)
> GEN_VEXT_VF(vfmax_vf_d, 8, 8, clearq)
--
Alex Bennée
- [RFC 23/65] target/riscv: rvv-0.9: floating-point classify instructions, (continued)
- [RFC 23/65] target/riscv: rvv-0.9: floating-point classify instructions, frank . chang, 2020/07/10
- [RFC 24/65] target/riscv: rvv-0.9: mask population count instruction, frank . chang, 2020/07/10
- [RFC 26/65] target/riscv: rvv-0.9: set-X-first mask bit instructions, frank . chang, 2020/07/10
- [RFC 30/65] target/riscv: rvv-0.9: floating-point scalar move instructions, frank . chang, 2020/07/10
- [RFC 34/65] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow, frank . chang, 2020/07/10
- [RFC 45/65] target/riscv: rvv-0.9: register gather instructions, frank . chang, 2020/07/10
- [RFC 47/65] target/riscv: rvv-0.9: floating-point slide instructions, frank . chang, 2020/07/10
- [RFC 52/65] target/riscv: rvv-0.9: widening floating-point reduction instructions, frank . chang, 2020/07/10
- [RFC 56/65] target/riscv: rvv-0.9: remove integer extract instruction, frank . chang, 2020/07/10
- [RFC 57/65] target/riscv: rvv-0.9: floating-point min/max instructions, frank . chang, 2020/07/10
- Re: [RFC 57/65] target/riscv: rvv-0.9: floating-point min/max instructions,
Alex Bennée <=
- [RFC 58/65] target/riscv: rvv-0.9: widening floating-point/integer type-convert, frank . chang, 2020/07/10
- [RFC 61/65] fpu: fix float16 nan check, frank . chang, 2020/07/10
- [RFC 62/65] fpu: add api to handle alternative sNaN propagation, frank . chang, 2020/07/10
- [RFC 64/65] target/riscv: use softfloat lib float16 comparison functions, frank . chang, 2020/07/10
- [RFC 10/65] target/riscv: rvv-0.9: remove MLEN calculations, frank . chang, 2020/07/10
- Re: [RFC 00/65] target/riscv: support vector extension v0.9, Alistair Francis, 2020/07/10