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[RFC 26/65] target/riscv: rvv-0.9: set-X-first mask bit instructions
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From: |
frank . chang |
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Subject: |
[RFC 26/65] target/riscv: rvv-0.9: set-X-first mask bit instructions |
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Date: |
Fri, 10 Jul 2020 18:48:40 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 6 ++---
target/riscv/insn_trans/trans_rvv.inc.c | 32 +++++++++++++------------
target/riscv/vector_helper.c | 4 ----
3 files changed, 20 insertions(+), 22 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b5b59fe6dd..37b2582981 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -575,9 +575,9 @@ vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
-vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
-vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
-vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm
+vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
+vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
+vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 2db7e7f58f..c1efb87e8d 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2758,22 +2758,24 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
#define GEN_M_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
- if (vext_check_isa_ill(s)) { \
- uint32_t data = 0; \
- gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ REQUIRE_RVV; \
+ VEXT_CHECK_ISA_ILL(s); \
+ require_vm(a->vm, a->rd); \
+ require(a->rd != a->rs2); \
\
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- data = FIELD_DP32(data, VDATA, VMA, s->vma); \
- tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
- vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
- cpu_env, 0, s->vlen / 8, data, fn); \
- gen_set_label(over); \
- return true; \
- } \
- return false; \
+ uint32_t data = 0; \
+ gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
+ TCGLabel *over = gen_new_label(); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
+ vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
+ cpu_env, 0, s->vlen / 8, data, fn); \
+ gen_set_label(over); \
+ return true; \
}
GEN_M_TRANS(vmsbf_m)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index f13f6c6dda..bc1363fb7d 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4675,7 +4675,6 @@ enum set_mask_type {
static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
uint32_t desc, enum set_mask_type type)
{
- uint32_t vlmax = env_archcpu(env)->cfg.vlen;
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
int i;
@@ -4705,9 +4704,6 @@ static void vmsetm(void *vd, void *v0, void *vs2,
CPURISCVState *env,
}
}
}
- for (; i < vlmax; i++) {
- vext_set_elem_mask(vd, i, 0);
- }
}
void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
--
2.17.1
- [RFC 59/65] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert, (continued)
- [RFC 59/65] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert, frank . chang, 2020/07/10
- [RFC 65/65] target/riscv: bump to RVV 0.9, frank . chang, 2020/07/10
- [RFC 01/65] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion, frank . chang, 2020/07/10
- [RFC 08/65] target/riscv: rvv-0.9: update mstatus_vs by tb_flags, frank . chang, 2020/07/10
- [RFC 16/65] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns, frank . chang, 2020/07/10
- [RFC 23/65] target/riscv: rvv-0.9: floating-point classify instructions, frank . chang, 2020/07/10
- [RFC 24/65] target/riscv: rvv-0.9: mask population count instruction, frank . chang, 2020/07/10
- [RFC 26/65] target/riscv: rvv-0.9: set-X-first mask bit instructions,
frank . chang <=
- [RFC 30/65] target/riscv: rvv-0.9: floating-point scalar move instructions, frank . chang, 2020/07/10
- [RFC 34/65] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow, frank . chang, 2020/07/10
- [RFC 45/65] target/riscv: rvv-0.9: register gather instructions, frank . chang, 2020/07/10
- [RFC 47/65] target/riscv: rvv-0.9: floating-point slide instructions, frank . chang, 2020/07/10
- [RFC 52/65] target/riscv: rvv-0.9: widening floating-point reduction instructions, frank . chang, 2020/07/10
- [RFC 56/65] target/riscv: rvv-0.9: remove integer extract instruction, frank . chang, 2020/07/10
- [RFC 57/65] target/riscv: rvv-0.9: floating-point min/max instructions, frank . chang, 2020/07/10
- [RFC 58/65] target/riscv: rvv-0.9: widening floating-point/integer type-convert, frank . chang, 2020/07/10
- [RFC 61/65] fpu: fix float16 nan check, frank . chang, 2020/07/10