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Re: [RFC 00/65] target/riscv: support vector extension v0.9

From: Frank Chang
Subject: Re: [RFC 00/65] target/riscv: support vector extension v0.9
Date: Mon, 13 Jul 2020 10:02:31 +0800

On Sat, Jul 11, 2020 at 5:53 AM Alistair Francis <alistair23@gmail.com> wrote:
On Fri, Jul 10, 2020 at 5:59 AM <frank.chang@sifive.com> wrote:
> From: Frank Chang <frank.chang@sifive.com>
> This patchset implements the vector extension v0.9 for RISC-V on QEMU.
> This patchset is sent as RFC because RVV v0.9 is still in draft state.
> However, as RVV v1.0 should be ratified soon and there shouldn't be
> critical changes between RVV v1.0 and RVV v0.9. We would like to have
> the community to review RVV v0.9 implementations. Once RVV v1.0 is
> ratified, we will then upgrade to RVV v1.0.
> You can change the cpu argument: vext_spec to v0.9 (i.e. vext_spec=v0.9)
> to run with RVV v0.9 instructions.


First off thanks for the patches!

QEMU has a policy of accepting draft specs as experimental. We
currently support the v0.7.1 Vector extension for example, so this
does not need to be an RFC and can be a full patch series that can be
merged into master.

I have applied the first few patches (PR should be out next week) and
they should be in the QEMU 5.1 release. QEMU is currently in a freeze
so I won't be able to merge this series for 5.1. In saying that please
feel free to continue to send patches to the list, they can still be

In general we would need to gracefully handle extension upgrades and
maintain backwards compatibility. This same principle doesn't apply to
experimental features though (such as the vector extension) so you are
free to remove support for the v0.7.1. For users who want v0.7.1
support they can always use the QEMU 5.1. release. Just make sure that
your series does not break bisectability.

Thanks again for the patches!


Hi Alistair,

Thanks for the review.

Currently I would prefer to drop 0.7.1 support because I don't know if there's
a good way to keep both 0.7.1 and 0.9 opcodes. I'm afraid it would cause the
encoding overlap while compiling with decodetree.

Does decodetree support any feature for multi-version opcodes?
Or if it can use something like C macros to compile with the opcodes by the vspec
user assigned? If there's any good way to keep both versions, then I can try to rearrange
my codes to support both vspecs.

Otherwise, I'll keep on my current approach to drop the support of v0.7.1 as the way
Richard has mentioned:
If you don't want to simultaneously support 0.7.1 and 0.9/1.0, then you should
simply remove 0.7.1 in the first patch, so that there's no confusion.

Any suggestion would be appreciated.

Frank Chang

> Chih-Min Chao (2):
>   fpu: fix float16 nan check
>   fpu: add api to handle alternative sNaN propagation
> Frank Chang (58):
>   target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
>   target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
>   target/riscv: fix return value of do_opivx_widen()
>   target/riscv: fix vill bit index in vtype register
>   target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec
>   target/riscv: rvv-0.9: remove MLEN calculations
>   target/riscv: rvv-0.9: add fractional LMUL, VTA and VMA
>   target/riscv: rvv-0.9: update check functions
>   target/riscv: rvv-0.9: configure instructions
>   target/riscv: rvv-0.9: stride load and store instructions
>   target/riscv: rvv-0.9: index load and store instructions
>   target/riscv: rvv-0.9: fix address index overflow bug of indexed
>     load/store insns
>   target/riscv: rvv-0.9: fault-only-first unit stride load
>   target/riscv: rvv-0.9: amo operations
>   target/riscv: rvv-0.9: load/store whole register instructions
>   target/riscv: rvv-0.9: update vext_max_elems() for load/store insns
>   target/riscv: rvv-0.9: take fractional LMUL into vector max elements
>     calculation
>   target/riscv: rvv-0.9: floating-point square-root instruction
>   target/riscv: rvv-0.9: floating-point classify instructions
>   target/riscv: rvv-0.9: mask population count instruction
>   target/riscv: rvv-0.9: find-first-set mask bit instruction
>   target/riscv: rvv-0.9: set-X-first mask bit instructions
>   target/riscv: rvv-0.9: iota instruction
>   target/riscv: rvv-0.9: element index instruction
>   target/riscv: rvv-0.9: integer scalar move instructions
>   target/riscv: rvv-0.9: floating-point scalar move instructions
>   target/riscv: rvv-0.9: whole register move instructions
>   target/riscv: rvv-0.9: integer extension instructions
>   target/riscv: rvv-0.9: single-width averaging add and subtract
>     instructions
>   target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow
>   target/riscv: rvv-0.9: narrowing integer right shift instructions
>   target/riscv: rvv-0.9: widening integer multiply-add instructions
>   target/riscv: rvv-0.9: quad-widening integer multiply-add instructions
>   target/riscv: rvv-0.9: integer merge and move instructions
>   target/riscv: rvv-0.9: single-width saturating add and subtract
>     instructions
>   target/riscv: rvv-0.9: integer comparison instructions
>   target/riscv: rvv-0.9: floating-point compare instructions
>   target/riscv: rvv-0.9: single-width integer reduction instructions
>   target/riscv: rvv-0.9: widening integer reduction instructions
>   target/riscv: rvv-0.9: mask-register logical instructions
>   target/riscv: rvv-0.9: register gather instructions
>   target/riscv: rvv-0.9: slide instructions
>   target/riscv: rvv-0.9: floating-point slide instructions
>   target/riscv: rvv-0.9: narrowing fixed-point clip instructions
>   target/riscv: rvv-0.9: floating-point move instructions
>   target/riscv: rvv-0.9: floating-point/integer type-convert
>     instructions
>   target/riscv: rvv-0.9: single-width floating-point reduction
>   target/riscv: rvv-0.9: widening floating-point reduction instructions
>   target/riscv: rvv-0.9: single-width scaling shift instructions
>   target/riscv: rvv-0.9: remove widening saturating scaled multiply-add
>   target/riscv: rvv-0.9: remove vmford.vv and vmford.vf
>   target/riscv: rvv-0.9: remove integer extract instruction
>   target/riscv: rvv-0.9: floating-point min/max instructions
>   target/riscv: rvv-0.9: widening floating-point/integer type-convert
>   target/riscv: rvv-0.9: narrowing floating-point/integer type-convert
>   softfloat: add fp16 and uint8/int8 interconvert functions
>   target/riscv: use softfloat lib float16 comparison functions
>   target/riscv: bump to RVV 0.9
> Kito Cheng (1):
>   fpu: implement full set compare for fp16
> LIU Zhiwei (4):
>   target/riscv: rvv-0.9: add vcsr register
>   target/riscv: rvv-0.9: add vector context status
>   target/riscv: rvv-0.9: update mstatus_vs by tb_flags
>   target/riscv: rvv-0.9: add vlenb register
>  fpu/softfloat-specialize.inc.c          |    4 +-
>  fpu/softfloat.c                         |  342 +++-
>  include/fpu/softfloat.h                 |   22 +
>  target/riscv/cpu.c                      |    9 +-
>  target/riscv/cpu.h                      |   68 +-
>  target/riscv/cpu_bits.h                 |    9 +
>  target/riscv/cpu_helper.c               |   13 +
>  target/riscv/csr.c                      |   53 +-
>  target/riscv/helper.h                   |  507 +++--
>  target/riscv/insn32-64.decode           |   18 +-
>  target/riscv/insn32.decode              |  282 +--
>  target/riscv/insn_trans/trans_rvv.inc.c | 2468 ++++++++++++++---------
>  target/riscv/internals.h                |   18 +-
>  target/riscv/translate.c                |   43 +-
>  target/riscv/vector_helper.c            | 2349 +++++++++++----------
>  15 files changed, 3833 insertions(+), 2372 deletions(-)
> --
> 2.17.1

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