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Re: [RFC 03/65] target/riscv: fix return value of do_opivx_widen()
From: |
Richard Henderson |
Subject: |
Re: [RFC 03/65] target/riscv: fix return value of do_opivx_widen() |
Date: |
Fri, 10 Jul 2020 09:14:56 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 |
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> do_opivx_widen() should return false if check function returns false.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Alistair, this one should be queued for 5.1 as a bug fix.
r~
- [RFC 00/65] target/riscv: support vector extension v0.9, frank . chang, 2020/07/10
- [RFC 27/65] target/riscv: rvv-0.9: iota instruction, frank . chang, 2020/07/10
- [RFC 37/65] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions, frank . chang, 2020/07/10
- [RFC 44/65] target/riscv: rvv-0.9: mask-register logical instructions, frank . chang, 2020/07/10
- [RFC 03/65] target/riscv: fix return value of do_opivx_widen(), frank . chang, 2020/07/10
- Re: [RFC 03/65] target/riscv: fix return value of do_opivx_widen(),
Richard Henderson <=
- [RFC 06/65] target/riscv: rvv-0.9: add vcsr register, frank . chang, 2020/07/10
- [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions, frank . chang, 2020/07/10
- [RFC 07/65] target/riscv: rvv-0.9: add vector context status, frank . chang, 2020/07/10
- [RFC 19/65] target/riscv: rvv-0.9: load/store whole register instructions, frank . chang, 2020/07/10
- [RFC 25/65] target/riscv: rvv-0.9: find-first-set mask bit instruction, frank . chang, 2020/07/10