Re: [RFC 02/65] target/riscv: correct the gvec IR called in gen_vec

qemu-riscv

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Re: [RFC 02/65] target/riscv: correct the gvec IR called in gen_vec_rsub

From:	Richard Henderson
Subject:	Re: [RFC 02/65] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
Date:	Fri, 10 Jul 2020 09:13:18 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0

On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
> 
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
>  target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Alistair, this one should be queued for 5.1 as a bug fix.


r~

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[RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions, (continued)
- [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions, frank . chang, 2020/07/10
  - Re: [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions, Richard Henderson, 2020/07/10
    - Re: [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions, Frank Chang, 2020/07/12
- [RFC 07/65] target/riscv: rvv-0.9: add vector context status, frank . chang, 2020/07/10
  - Re: [RFC 07/65] target/riscv: rvv-0.9: add vector context status, Richard Henderson, 2020/07/10
  - Re: [RFC 07/65] target/riscv: rvv-0.9: add vector context status, Richard Henderson, 2020/07/10
- [RFC 19/65] target/riscv: rvv-0.9: load/store whole register instructions, frank . chang, 2020/07/10
- [RFC 25/65] target/riscv: rvv-0.9: find-first-set mask bit instruction, frank . chang, 2020/07/10
- [RFC 31/65] target/riscv: rvv-0.9: whole register move instructions, frank . chang, 2020/07/10
- [RFC 02/65] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64(), frank . chang, 2020/07/10
  - Re: [RFC 02/65] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64(), Richard Henderson <=
- [RFC 04/65] target/riscv: fix vill bit index in vtype register, frank . chang, 2020/07/10
  - Re: [RFC 04/65] target/riscv: fix vill bit index in vtype register, Richard Henderson, 2020/07/10
- [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, frank . chang, 2020/07/10
  - Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Richard Henderson, 2020/07/10
    - Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Frank Chang, 2020/07/13
    - Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, LIU Zhiwei, 2020/07/13
    - Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Frank Chang, 2020/07/14
    - Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Richard Henderson, 2020/07/14
    - Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, Frank Chang, 2020/07/14
    - Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, LIU Zhiwei, 2020/07/14

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