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[RFC 06/65] target/riscv: rvv-0.9: add vcsr register
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From: |
frank . chang |
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Subject: |
[RFC 06/65] target/riscv: rvv-0.9: add vcsr register |
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Date: |
Fri, 10 Jul 2020 18:48:20 +0800 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu_bits.h | 7 +++++++
target/riscv/csr.c | 21 +++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8117e8b5a7..202440e5eb 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -60,9 +60,16 @@
#define CSR_VSTART 0x008
#define CSR_VXSAT 0x009
#define CSR_VXRM 0x00a
+#define CSR_VCSR 0x00f
#define CSR_VL 0xc20
#define CSR_VTYPE 0xc21
+/* VCSR fields */
+#define VCSR_VXSAT_SHIFT 0
+#define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT)
+#define VCSR_VXRM_SHIFT 1
+#define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT)
+
/* User Timers and Counters */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ac01c835e1..34ce509e64 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -238,6 +238,26 @@ static int write_vstart(CPURISCVState *env, int csrno,
target_ulong val)
return 0;
}
+static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
+ return 0;
+}
+
+static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
+{
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return -1;
+ }
+ env->mstatus |= MSTATUS_VS;
+#endif
+
+ env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
+ env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
+ return 0;
+}
+
/* User Timers and Counters */
static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
{
@@ -1255,6 +1275,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_VSTART] = { vs, read_vstart, write_vstart },
[CSR_VXSAT] = { vs, read_vxsat, write_vxsat },
[CSR_VXRM] = { vs, read_vxrm, write_vxrm },
+ [CSR_VCSR] = { vs, read_vcsr, write_vcsr },
[CSR_VL] = { vs, read_vl },
[CSR_VTYPE] = { vs, read_vtype },
/* User Timers and Counters */
--
2.17.1
- [RFC 00/65] target/riscv: support vector extension v0.9, frank . chang, 2020/07/10
- [RFC 27/65] target/riscv: rvv-0.9: iota instruction, frank . chang, 2020/07/10
- [RFC 37/65] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions, frank . chang, 2020/07/10
- [RFC 44/65] target/riscv: rvv-0.9: mask-register logical instructions, frank . chang, 2020/07/10
- [RFC 03/65] target/riscv: fix return value of do_opivx_widen(), frank . chang, 2020/07/10
- [RFC 06/65] target/riscv: rvv-0.9: add vcsr register,
frank . chang <=
- [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions, frank . chang, 2020/07/10
- [RFC 07/65] target/riscv: rvv-0.9: add vector context status, frank . chang, 2020/07/10
- [RFC 19/65] target/riscv: rvv-0.9: load/store whole register instructions, frank . chang, 2020/07/10
- [RFC 25/65] target/riscv: rvv-0.9: find-first-set mask bit instruction, frank . chang, 2020/07/10
- [RFC 31/65] target/riscv: rvv-0.9: whole register move instructions, frank . chang, 2020/07/10