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[Qemu-riscv] [PULL 26/48] riscv: sifive_e: Drop sifive_mmio_emulate()
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 26/48] riscv: sifive_e: Drop sifive_mmio_emulate() |
Date: |
Wed, 18 Sep 2019 07:56:18 -0700 |
From: Bin Meng <address@hidden>
Use create_unimplemented_device() instead.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/Kconfig | 1 +
hw/riscv/sifive_e.c | 23 ++++++++---------------
2 files changed, 9 insertions(+), 15 deletions(-)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 8674211085..33e54b031d 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -12,6 +12,7 @@ config SIFIVE_E
bool
select HART
select SIFIVE
+ select UNIMP
config SIFIVE_U
bool
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 1428a99fce..0f9d641a0e 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -36,6 +36,7 @@
#include "hw/loader.h"
#include "hw/sysbus.h"
#include "hw/char/serial.h"
+#include "hw/misc/unimp.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_plic.h"
@@ -74,14 +75,6 @@ static const struct MemmapEntry {
[SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
};
-static void sifive_mmio_emulate(MemoryRegion *parent, const char *name,
- uintptr_t offset, uintptr_t length)
-{
- MemoryRegion *mock_mmio = g_new(MemoryRegion, 1);
- memory_region_init_ram(mock_mmio, NULL, name, length, &error_fatal);
- memory_region_add_subregion(parent, offset, mock_mmio);
-}
-
static void riscv_sifive_e_init(MachineState *machine)
{
const struct MemmapEntry *memmap = sifive_e_memmap;
@@ -172,7 +165,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev,
Error **errp)
sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
memmap[SIFIVE_E_CLINT].size, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
- sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
+ create_unimplemented_device("riscv.sifive.e.aon",
memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
@@ -199,19 +192,19 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev,
Error **errp)
sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
- sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0",
+ create_unimplemented_device("riscv.sifive.e.qspi0",
memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);
- sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0",
+ create_unimplemented_device("riscv.sifive.e.pwm0",
memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);
sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
- sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1",
+ create_unimplemented_device("riscv.sifive.e.qspi1",
memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);
- sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1",
+ create_unimplemented_device("riscv.sifive.e.pwm1",
memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size);
- sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi2",
+ create_unimplemented_device("riscv.sifive.e.qspi2",
memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size);
- sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm2",
+ create_unimplemented_device("riscv.sifive.e.pwm2",
memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);
/* Flash memory */
--
2.21.0
- [Qemu-riscv] [PULL 16/48] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, (continued)
- [Qemu-riscv] [PULL 16/48] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 17/48] riscv: hw: Remove not needed PLIC properties in device tree, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 18/48] riscv: hw: Change create_fdt() to return void, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 19/48] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 20/48] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 21/48] riscv: roms: Remove executable attribute of opensbi images, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 22/48] riscv: sifive_u: Remove the unnecessary include of prci header, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 24/48] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 23/48] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 25/48] riscv: sifive_e: prci: Update the PRCI register block size, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 26/48] riscv: sifive_e: Drop sifive_mmio_emulate(),
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 29/48] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 27/48] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 32/48] riscv: sifive_u: Update PLIC hart topology configuration string, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 28/48] riscv: hart: Extract hart realize to a separate routine, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 30/48] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 31/48] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 33/48] riscv: sifive: Implement PRCI model for FU540, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 36/48] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 34/48] riscv: sifive_u: Generate hfclk and rtcclk nodes, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 37/48] riscv: sifive_u: Update UART base addresses and IRQs, Palmer Dabbelt, 2019/09/18