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[Qemu-riscv] [PULL 37/48] riscv: sifive_u: Update UART base addresses an
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From: |
Palmer Dabbelt |
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Subject: |
[Qemu-riscv] [PULL 37/48] riscv: sifive_u: Update UART base addresses and IRQs |
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Date: |
Wed, 18 Sep 2019 07:56:29 -0700 |
From: Bin Meng <address@hidden>
This updates the UART base address and IRQs to match the hardware.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Jonathan Behrens <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Chih-Min Chao <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_u.c | 4 ++--
include/hw/riscv/sifive_u.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 9e698a11c4..b66eaef607 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -62,8 +62,8 @@ static const struct MemmapEntry {
[SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
[SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
[SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
- [SIFIVE_U_UART0] = { 0x10013000, 0x1000 },
- [SIFIVE_U_UART1] = { 0x10023000, 0x1000 },
+ [SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
+ [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
[SIFIVE_U_GEM] = { 0x100900FC, 0x2000 },
};
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index bb46745356..7dfd1cb22e 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -65,8 +65,8 @@ enum {
};
enum {
- SIFIVE_U_UART0_IRQ = 3,
- SIFIVE_U_UART1_IRQ = 4,
+ SIFIVE_U_UART0_IRQ = 4,
+ SIFIVE_U_UART1_IRQ = 5,
SIFIVE_U_GEM_IRQ = 0x35
};
--
2.21.0
- [Qemu-riscv] [PULL 26/48] riscv: sifive_e: Drop sifive_mmio_emulate(), (continued)
- [Qemu-riscv] [PULL 26/48] riscv: sifive_e: Drop sifive_mmio_emulate(), Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 29/48] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 27/48] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 32/48] riscv: sifive_u: Update PLIC hart topology configuration string, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 28/48] riscv: hart: Extract hart realize to a separate routine, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 30/48] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 31/48] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 33/48] riscv: sifive: Implement PRCI model for FU540, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 36/48] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 34/48] riscv: sifive_u: Generate hfclk and rtcclk nodes, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 37/48] riscv: sifive_u: Update UART base addresses and IRQs,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 38/48] riscv: sifive_u: Change UART node name in device tree, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 35/48] riscv: sifive_u: Add PRCI block to the SoC, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 41/48] riscv: sifive_u: Instantiate OTP memory with a serial number, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 40/48] riscv: sifive: Implement a model for SiFive FU540 OTP, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 43/48] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 39/48] riscv: roms: Update default bios for sifive_u machine, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 45/48] target/riscv: Use both register name and ABI name, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 42/48] riscv: sifive_u: Fix broken GEM support, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 44/48] riscv: sifive_u: Update model and compatible strings in device tree, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 46/48] target/riscv: Fix mstatus dirty mask, Palmer Dabbelt, 2019/09/18