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[Qemu-riscv] [PULL 19/48] riscv: hw: Change to use qemu_log_mask(LOG_GUE
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 19/48] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead |
Date: |
Wed, 18 Sep 2019 07:56:11 -0700 |
From: Bin Meng <address@hidden>
Replace the call to hw_error() with qemu_log_mask(LOG_GUEST_ERROR,...)
in various sifive models.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_prci.c | 8 +++++---
hw/riscv/sifive_test.c | 5 +++--
hw/riscv/sifive_uart.c | 9 +++++----
3 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c
index 562bc3dc4c..982fbb26fd 100644
--- a/hw/riscv/sifive_prci.c
+++ b/hw/riscv/sifive_prci.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "hw/sysbus.h"
+#include "qemu/log.h"
#include "qemu/module.h"
#include "target/riscv/cpu.h"
#include "hw/hw.h"
@@ -38,7 +39,8 @@ static uint64_t sifive_prci_read(void *opaque, hwaddr addr,
unsigned int size)
case SIFIVE_PRCI_PLLOUTDIV:
return s->plloutdiv;
}
- hw_error("%s: read: addr=0x%x\n", __func__, (int)addr);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%x\n",
+ __func__, (int)addr);
return 0;
}
@@ -66,8 +68,8 @@ static void sifive_prci_write(void *opaque, hwaddr addr,
s->plloutdiv = (uint32_t) val64;
break;
default:
- hw_error("%s: bad write: addr=0x%x v=0x%x\n",
- __func__, (int)addr, (int)val64);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n",
+ __func__, (int)addr, (int)val64);
}
}
diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
index 711740939e..aa544e7428 100644
--- a/hw/riscv/sifive_test.c
+++ b/hw/riscv/sifive_test.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "hw/sysbus.h"
+#include "qemu/log.h"
#include "qemu/module.h"
#include "sysemu/runstate.h"
#include "target/riscv/cpu.h"
@@ -49,8 +50,8 @@ static void sifive_test_write(void *opaque, hwaddr addr,
break;
}
}
- hw_error("%s: write: addr=0x%x val=0x%016" PRIx64 "\n",
- __func__, (int)addr, val64);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: write: addr=0x%x val=0x%016" PRIx64
"\n",
+ __func__, (int)addr, val64);
}
static const MemoryRegionOps sifive_test_ops = {
diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c
index 9de42b1680..215990b443 100644
--- a/hw/riscv/sifive_uart.c
+++ b/hw/riscv/sifive_uart.c
@@ -18,6 +18,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
+#include "qemu/log.h"
#include "hw/sysbus.h"
#include "chardev/char.h"
#include "chardev/char-fe.h"
@@ -95,8 +96,8 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
return s->div;
}
- hw_error("%s: bad read: addr=0x%x\n",
- __func__, (int)addr);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read: addr=0x%x\n",
+ __func__, (int)addr);
return 0;
}
@@ -127,8 +128,8 @@ uart_write(void *opaque, hwaddr addr,
s->div = val64;
return;
}
- hw_error("%s: bad write: addr=0x%x v=0x%x\n",
- __func__, (int)addr, (int)value);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n",
+ __func__, (int)addr, (int)value);
}
static const MemoryRegionOps uart_ops = {
--
2.21.0
- [Qemu-riscv] [PULL 09/48] riscv: rv32: Root page table address can be larger than 32-bit, (continued)
- [Qemu-riscv] [PULL 09/48] riscv: rv32: Root page table address can be larger than 32-bit, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 11/48] riscv: Resolve full path of the given bios image, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 13/48] riscv: sifive_test: Add reset functionality, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 12/48] riscv: hmp: Add a command to show virtual memory mappings, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 14/48] riscv: hw: Remove duplicated "hw/hw.h" inclusion, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 15/48] riscv: hw: Remove superfluous "linux, phandle" property, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 16/48] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 17/48] riscv: hw: Remove not needed PLIC properties in device tree, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 18/48] riscv: hw: Change create_fdt() to return void, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 19/48] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 20/48] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 21/48] riscv: roms: Remove executable attribute of opensbi images, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 22/48] riscv: sifive_u: Remove the unnecessary include of prci header, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 24/48] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 23/48] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 25/48] riscv: sifive_e: prci: Update the PRCI register block size, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 26/48] riscv: sifive_e: Drop sifive_mmio_emulate(), Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 29/48] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 27/48] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 32/48] riscv: sifive_u: Update PLIC hart topology configuration string, Palmer Dabbelt, 2019/09/18