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[Qemu-riscv] [PATCH v8 17/32] riscv: hart: Add a "hartid-base" property
From: |
Bin Meng |
Subject: |
[Qemu-riscv] [PATCH v8 17/32] riscv: hart: Add a "hartid-base" property to RISC-V hart array |
Date: |
Fri, 6 Sep 2019 09:20:04 -0700 |
At present each hart's hartid in a RISC-V hart array is assigned
the same value of its index in the hart array. But for a system
that has multiple hart arrays, this is not the case any more.
Add a new "hartid-base" property so that hartid number can be
assigned based on the property value.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
Changes in v8: None
Changes in v7:
- use `s->hartid_base + idx` directly
Changes in v6:
- use s->hartid_base directly, instead of an extra variable
Changes in v5: None
Changes in v4:
- new patch to add a "hartid-base" property to RISC-V hart array
Changes in v3: None
Changes in v2: None
hw/riscv/riscv_hart.c | 3 ++-
include/hw/riscv/riscv_hart.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index 6620e41..5b98227 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -29,6 +29,7 @@
static Property riscv_harts_props[] = {
DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
+ DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
DEFINE_PROP_END_OF_LIST(),
};
@@ -47,7 +48,7 @@ static void riscv_hart_realize(RISCVHartArrayState *s, int
idx,
object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx],
sizeof(RISCVCPU), cpu_type,
&error_abort, NULL);
- s->harts[idx].env.mhartid = idx;
+ s->harts[idx].env.mhartid = s->hartid_base + idx;
qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
object_property_set_bool(OBJECT(&s->harts[idx]), true,
"realized", &err);
diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
index 3b52b50..c75856f 100644
--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -35,6 +35,7 @@ typedef struct RISCVHartArrayState {
/*< public >*/
uint32_t num_harts;
+ uint32_t hartid_base;
char *cpu_type;
RISCVCPU *harts;
} RISCVHartArrayState;
--
2.7.4
- [Qemu-riscv] [PATCH v8 07/32] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead, (continued)
- [Qemu-riscv] [PATCH v8 07/32] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 09/32] riscv: roms: Remove executable attribute of opensbi images, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 06/32] riscv: hw: Change create_fdt() to return void, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 13/32] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 10/32] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 16/32] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 14/32] riscv: sifive_e: Drop sifive_mmio_emulate(), Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 15/32] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 11/32] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 17/32] riscv: hart: Add a "hartid-base" property to RISC-V hart array,
Bin Meng <=
- [Qemu-riscv] [PATCH v8 22/32] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/09/06
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/13
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/09/13
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/14
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/09/15
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/15
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Jonathan Behrens, 2019/09/15
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/15
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/09/16