[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of
From: |
Bin Meng |
Subject: |
[Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2 |
Date: |
Fri, 6 Sep 2019 09:20:05 -0700 |
It is not useful if we only have one management CPU.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- use management cpu count + 1 for the min_cpus
Changes in v2:
- update the file header to indicate at least 2 harts are created
hw/riscv/sifive_u.c | 4 +++-
include/hw/riscv/sifive_u.h | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 2947e06..2023b71 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -10,7 +10,8 @@
* 1) CLINT (Core Level Interruptor)
* 2) PLIC (Platform Level Interrupt Controller)
*
- * This board currently uses a hardcoded devicetree that indicates one hart.
+ * This board currently generates devicetree dynamically that indicates at
least
+ * two harts.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -433,6 +434,7 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
* management CPU.
*/
mc->max_cpus = 4;
+ mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
}
DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index f25bad8..6d22741 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -69,6 +69,8 @@ enum {
SIFIVE_U_GEM_CLOCK_FREQ = 125000000
};
+#define SIFIVE_U_MANAGEMENT_CPU_COUNT 1
+
#define SIFIVE_U_PLIC_HART_CONFIG "MS"
#define SIFIVE_U_PLIC_NUM_SOURCES 54
#define SIFIVE_U_PLIC_NUM_PRIORITIES 7
--
2.7.4
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 09/32] riscv: roms: Remove executable attribute of opensbi images, (continued)
- [Qemu-riscv] [PATCH v8 06/32] riscv: hw: Change create_fdt() to return void, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 13/32] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 10/32] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 16/32] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 14/32] riscv: sifive_e: Drop sifive_mmio_emulate(), Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 15/32] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 11/32] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 17/32] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 22/32] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2,
Bin Meng <=
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/13
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/09/13
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/14
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/09/15
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/15
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Jonathan Behrens, 2019/09/15
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/15
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/09/16
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Alistair Francis, 2019/09/16
[Qemu-riscv] [PATCH v8 20/32] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/09/06