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[Qemu-riscv] [PATCH v8 10/32] riscv: sifive_u: Remove the unnecessary in
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From: |
Bin Meng |
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Subject: |
[Qemu-riscv] [PATCH v8 10/32] riscv: sifive_u: Remove the unnecessary include of prci header |
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Date: |
Fri, 6 Sep 2019 09:19:57 -0700 |
sifive_u machine does not use PRCI as of today. Remove the prci
header inclusion.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_u.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 32d8cee..2947e06 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -38,7 +38,6 @@
#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_uart.h"
-#include "hw/riscv/sifive_prci.h"
#include "hw/riscv/sifive_u.h"
#include "hw/riscv/boot.h"
#include "chardev/char.h"
--
2.7.4
- [Qemu-riscv] [PATCH v8 05/32] riscv: hw: Remove not needed PLIC properties in device tree, (continued)
- [Qemu-riscv] [PATCH v8 05/32] riscv: hw: Remove not needed PLIC properties in device tree, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 03/32] riscv: hw: Remove superfluous "linux, phandle" property, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 04/32] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 08/32] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 12/32] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 07/32] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 09/32] riscv: roms: Remove executable attribute of opensbi images, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 06/32] riscv: hw: Change create_fdt() to return void, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 13/32] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 10/32] riscv: sifive_u: Remove the unnecessary include of prci header,
Bin Meng <=
- [Qemu-riscv] [PATCH v8 16/32] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 14/32] riscv: sifive_e: Drop sifive_mmio_emulate(), Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 15/32] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 11/32] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 17/32] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 22/32] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/09/06