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[PULL 21/23] ppc/pnv: Remove LSI on the PCIE host bridge
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 21/23] ppc/pnv: Remove LSI on the PCIE host bridge |
Date: |
Wed, 20 Apr 2022 19:13:27 -0300 |
From: Frederic Barrat <fbarrat@linux.ibm.com>
The phb3/phb4/phb5 root ports inherit from the default PCIE root port
implementation, which requests a LSI interrupt (#INTA). On real
hardware (POWER8/POWER9/POWER10), there is no such LSI. This patch
corrects it so that it matches the hardware.
As a consequence, the device tree previously generated was bogus, as
the root bridge LSI was not properly mapped. On some
implementation (powernv9), it was leading to inconsistent interrupt
controller (xive) data. With this patch, it is now clean.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220408131303.147840-3-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/pci-host/pnv_phb3.c | 1 +
hw/pci-host/pnv_phb4.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
index 4e68ad4f03..3f03467dde 100644
--- a/hw/pci-host/pnv_phb3.c
+++ b/hw/pci-host/pnv_phb3.c
@@ -1161,6 +1161,7 @@ static void pnv_phb3_root_port_realize(DeviceState *dev,
Error **errp)
error_propagate(errp, local_err);
return;
}
+ pci_config_set_interrupt_pin(pci->config, 0);
}
static void pnv_phb3_root_port_class_init(ObjectClass *klass, void *data)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 3c4c2dace0..13ba9e45d8 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1771,6 +1771,7 @@ static void pnv_phb4_root_port_reset(DeviceState *dev)
pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1);
pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */
pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff);
+ pci_config_set_interrupt_pin(conf, 0);
}
static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp)
--
2.35.1
- [PULL 11/23] qemu/int128: add int128_urshift, (continued)
- [PULL 11/23] qemu/int128: add int128_urshift, Daniel Henrique Barboza, 2022/04/20
- [PULL 12/23] softfloat: add uint128_to_float128, Daniel Henrique Barboza, 2022/04/20
- [PULL 13/23] softfloat: add int128_to_float128, Daniel Henrique Barboza, 2022/04/20
- [PULL 14/23] softfloat: add float128_to_uint128, Daniel Henrique Barboza, 2022/04/20
- [PULL 15/23] softfloat: add float128_to_int128, Daniel Henrique Barboza, 2022/04/20
- [PULL 16/23] target/ppc: implement xscv[su]qqp, Daniel Henrique Barboza, 2022/04/20
- [PULL 17/23] target/ppc: implement xscvqp[su]qz, Daniel Henrique Barboza, 2022/04/20
- [PULL 18/23] hw/ppc/ppc405_boards: Initialize g_autofree pointer, Daniel Henrique Barboza, 2022/04/20
- [PULL 19/23] ppc/vof: Fix uninitialized string tracing, Daniel Henrique Barboza, 2022/04/20
- [PULL 20/23] pcie: Don't try triggering a LSI when not defined, Daniel Henrique Barboza, 2022/04/20
- [PULL 21/23] ppc/pnv: Remove LSI on the PCIE host bridge,
Daniel Henrique Barboza <=
- [PULL 22/23] target/ppc: Add two missing register callbacks on POWER10, Daniel Henrique Barboza, 2022/04/20
- [PULL 23/23] hw/ppc: change indentation to spaces from TABs, Daniel Henrique Barboza, 2022/04/20
- Re: [PULL 00/23] ppc queue, Richard Henderson, 2022/04/21