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[Qemu-ppc] [PULL 24/67] target-ppc: implement xsnegqp instruction
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 24/67] target-ppc: implement xsnegqp instruction |
Date: |
Thu, 12 Jan 2017 13:02:44 +1100 |
From: Nikunj A Dadhania <address@hidden>
xsnegqp: VSX Scalar Negate Quad-Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate/vsx-impl.inc.c | 4 ++++
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index 808ee48..e74e16e 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -633,6 +633,9 @@ static void glue(gen_, name)(DisasContext *ctx)
\
case OP_NABS: \
tcg_gen_or_i64(xbh, xbh, sgm); \
break; \
+ case OP_NEG: \
+ tcg_gen_xor_i64(xbh, xbh, sgm); \
+ break; \
} \
tcg_gen_mov_i64(cpu_vsrh(xt), xbh); \
tcg_gen_mov_i64(cpu_vsrl(xt), xbl); \
@@ -643,6 +646,7 @@ static void glue(gen_, name)(DisasContext *ctx)
\
VSX_SCALAR_MOVE_QP(xsabsqp, OP_ABS, SGN_MASK_DP)
VSX_SCALAR_MOVE_QP(xsnabsqp, OP_NABS, SGN_MASK_DP)
+VSX_SCALAR_MOVE_QP(xsnegqp, OP_NEG, SGN_MASK_DP)
#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
static void glue(gen_, name)(DisasContext * ctx) \
diff --git a/target/ppc/translate/vsx-ops.inc.c
b/target/ppc/translate/vsx-ops.inc.c
index daf6a56..f7132b4 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -98,6 +98,7 @@ GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
GEN_VSX_XFORM_300_EO(xsabsqp, 0x04, 0x19, 0x00, 0x00000001),
GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
+GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
--
2.9.3
- [Qemu-ppc] [PULL 00/67] ppc-for-2.9 queue 20170112, David Gibson, 2017/01/11
- [Qemu-ppc] [PULL 04/67] target-ppc: Fix xscmpodp and xscmpudp instructions, David Gibson, 2017/01/11
- [Qemu-ppc] [PULL 01/67] disas/ppc: Fix indefinite articles in comments, David Gibson, 2017/01/11
- [Qemu-ppc] [PULL 08/67] target-ppc: implement stxsd and stxssp, David Gibson, 2017/01/11
- [Qemu-ppc] [PULL 07/67] target-ppc: implement lxsd and lxssp instructions, David Gibson, 2017/01/11
- [Qemu-ppc] [PULL 09/67] target-ppc: implement lxv/lxvx and stxv/stxvx, David Gibson, 2017/01/11
- [Qemu-ppc] [PULL 24/67] target-ppc: implement xsnegqp instruction,
David Gibson <=
- [Qemu-ppc] [PULL 13/67] target-ppc: Implement bcdsetsgn. instruction, David Gibson, 2017/01/11
- [Qemu-ppc] [PULL 03/67] target-ppc: rename CRF_* defines as CRF_*_BIT, David Gibson, 2017/01/11
- [Qemu-ppc] [PULL 06/67] target-ppc: Add xscmpoqp and xscmpuqp instructions, David Gibson, 2017/01/11
- [Qemu-ppc] [PULL 05/67] target-ppc: Add xscmpexp[dp, qp] instructions, David Gibson, 2017/01/11
- [Qemu-ppc] [PULL 02/67] target-ppc: Consolidate instruction decode helpers, David Gibson, 2017/01/11
- [Qemu-ppc] [PULL 15/67] pseries: Always use core objects for CPU construction, David Gibson, 2017/01/11
- [Qemu-ppc] [PULL 10/67] target-ppc: Implement bcdcfsq. instruction, David Gibson, 2017/01/11
- [Qemu-ppc] [PULL 23/67] target-ppc: Implement bcd_is_valid function, David Gibson, 2017/01/11
- [Qemu-ppc] [PULL 25/67] target-ppc: implement xscpsgnqp instruction, David Gibson, 2017/01/11
- [Qemu-ppc] [PULL 11/67] target-ppc: Implement bcdctsq. instruction, David Gibson, 2017/01/11