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Re: [Qemu-ppc] [PATCH 3/4] target-ppc: add vrldnmi and vrlwmi instructio
From: |
Nikunj A Dadhania |
Subject: |
Re: [Qemu-ppc] [PATCH 3/4] target-ppc: add vrldnmi and vrlwmi instructions |
Date: |
Wed, 26 Oct 2016 10:14:06 +0530 |
User-agent: |
Notmuch/0.21 (https://notmuchmail.org) Emacs/25.0.94.1 (x86_64-redhat-linux-gnu) |
Richard Henderson <address@hidden> writes:
> On 10/24/2016 11:02 PM, Nikunj A Dadhania wrote:
>> Richard Henderson <address@hidden> writes:
>>
>>
>>> We already have rol32 and rol64.
>>>
>>> Which I see are broken for shift == 0.
>>
>> I tried with different shift (including 0) in a test program, and the
>> result is as expected:
>>
>> 0: ccddeeff
>>
>> static inline unsigned int rol32(unsigned int word, unsigned int shift)
>> {
>> return (word << shift) | (word >> (32 - shift));
>> }
>
> Technically, a shift by 32 is invalid. Practically, there are two common
> cases: shift >= 32 produces zero and shift is truncated to the word size, both
> of which produce the correct results here.
>
> That said, there's also the case of clang's sanitizers, which will in fact
> signal this as a runtime error.
In that case, will send patch updating them as part of my next revision
Regards
Nikunj
- [Qemu-ppc] [PATCH 2/4] target-ppc: add vmul10[u, eu, cu, ecu]q instructions, (continued)
- [Qemu-ppc] [PATCH 2/4] target-ppc: add vmul10[u, eu, cu, ecu]q instructions, Nikunj A Dadhania, 2016/10/24
- [Qemu-ppc] [PATCH 3/4] target-ppc: add vrldnmi and vrlwmi instructions, Nikunj A Dadhania, 2016/10/24
- Re: [Qemu-ppc] [PATCH 3/4] target-ppc: add vrldnmi and vrlwmi instructions, Nikunj A Dadhania, 2016/10/25
- Re: [Qemu-ppc] [PATCH 3/4] target-ppc: add vrldnmi and vrlwmi instructions, Richard Henderson, 2016/10/25
- Re: [Qemu-ppc] [PATCH 3/4] target-ppc: add vrldnmi and vrlwmi instructions,
Nikunj A Dadhania <=
[Qemu-ppc] [PATCH 4/4] target-ppc: add vrldnm and vrlwnm instructions, Nikunj A Dadhania, 2016/10/24