Re: [Qemu-ppc] [PATCH 3/4] target-ppc: add vrldnmi and vrlwmi instructions

[Richard Henderson]

On 10/24/2016 11:02 PM, Nikunj A Dadhania wrote:
> Richard Henderson <address@hidden> writes:
> 
> 
>> We already have rol32 and rol64.
>>
>> Which I see are broken for shift == 0.
> 
> I tried with different shift (including 0) in a test program, and the
> result is as expected:
> 
> 0: ccddeeff
> 
> static inline unsigned int rol32(unsigned int word, unsigned int shift)
> {
>   return (word << shift) | (word >> (32 - shift));
> }

Technically, a shift by 32 is invalid.  Practically, there are two common
cases: shift >= 32 produces zero and shift is truncated to the word size, both
of which produce the correct results here.

That said, there's also the case of clang's sanitizers, which will in fact
signal this as a runtime error.


r~