qemu-ppc
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-ppc] [PATCH 3/4] target-ppc: add vrldnmi and vrlwmi instructio


From: Richard Henderson
Subject: Re: [Qemu-ppc] [PATCH 3/4] target-ppc: add vrldnmi and vrlwmi instructions
Date: Tue, 25 Oct 2016 09:33:09 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0

On 10/24/2016 11:02 PM, Nikunj A Dadhania wrote:
> Richard Henderson <address@hidden> writes:
> 
> 
>> We already have rol32 and rol64.
>>
>> Which I see are broken for shift == 0.
> 
> I tried with different shift (including 0) in a test program, and the
> result is as expected:
> 
> 0: ccddeeff
> 
> static inline unsigned int rol32(unsigned int word, unsigned int shift)
> {
>   return (word << shift) | (word >> (32 - shift));
> }

Technically, a shift by 32 is invalid.  Practically, there are two common
cases: shift >= 32 produces zero and shift is truncated to the word size, both
of which produce the correct results here.

That said, there's also the case of clang's sanitizers, which will in fact
signal this as a runtime error.


r~



reply via email to

[Prev in Thread] Current Thread [Next in Thread]