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Re: [Qemu-ppc] [PATCH 4/4] spapr: Add support for time base offset migra

From: Benjamin Herrenschmidt
Subject: Re: [Qemu-ppc] [PATCH 4/4] spapr: Add support for time base offset migration
Date: Mon, 14 Apr 2014 21:14:44 +1000

On Mon, 2014-04-14 at 17:12 +1000, Alexey Kardashevskiy wrote:
> Our additional PHBs require @index property which is used to calculate
> base
> MMIO and IO ranges. That we could use for LSI/MSI too.

That works. We need to decide how much interrupt "space" we give to

The HW on P8 does 2048 MSIs plus the LSIs but we don't have to copy
that. The HW does that many because it can be split into 256 PE's but
our virtual PHBs represent a single PE#.

I think 4 LSIs + 256 MSIs is a reasonable number and should be fairly
future proof.

The numbers can be interleaved. IE the number space can be made to
look like

        PHB0 LSIs
        PHB1 LSIs
        PHB2 LSIs
        PHB0 MSIs
        PHB1 MSIs
        PHB2 MSIs

So the numbering remains compact (I would recommend doing that so the
ranges themselves remains power-of-2 sized).

I don't remember how we divide our interrupts into ranges/BUIDs
internally, so we might need to chose something that matches what we
do there a bit better, we'll see.


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