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[PATCH v4 6/7] target/riscv: Make the short cut really work in pmp_hart_
From: |
Weiwei Li |
Subject: |
[PATCH v4 6/7] target/riscv: Make the short cut really work in pmp_hart_has_privs |
Date: |
Sat, 22 Apr 2023 21:03:28 +0800 |
Return the result directly for short cut, since we needn't do the
following check on the PMP entries if there is no PMP rules.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/pmp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 0cef9e3e1d..b0f1b0a715 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -319,6 +319,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong
addr,
allowed_privs, mode)) {
ret = MAX_RISCV_PMPS;
}
+ return ret;
}
if (size == 0) {
--
2.25.1
- [PATCH v4 0/7] target/riscv: Fix PMP related problem, Weiwei Li, 2023/04/22
- [PATCH v4 3/7] target/riscv: Flush TLB when pmpaddr is updated, Weiwei Li, 2023/04/22
- [PATCH v4 2/7] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp, Weiwei Li, 2023/04/22
- [PATCH v4 4/7] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes, Weiwei Li, 2023/04/22
- [PATCH v4 5/7] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1, Weiwei Li, 2023/04/22
- [PATCH v4 1/7] target/riscv: Update pmp_get_tlb_size(), Weiwei Li, 2023/04/22
- [PATCH v4 7/7] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write, Weiwei Li, 2023/04/22
- [PATCH v4 6/7] target/riscv: Make the short cut really work in pmp_hart_has_privs,
Weiwei Li <=