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[PATCH v4 7/7] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_wr
From: |
Weiwei Li |
Subject: |
[PATCH v4 7/7] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write |
Date: |
Sat, 22 Apr 2023 21:03:29 +0800 |
Use pmp_update_rule_addr() and pmp_update_rule_nums() separately to
update rule nums only once for each pmpcfg_csr_write. Then we can also
move tlb_flush into pmp_update_rule_nums().
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/pmp.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index b0f1b0a715..5b765a9807 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -121,7 +121,7 @@ static bool pmp_write_cfg(CPURISCVState *env, uint32_t
pmp_index, uint8_t val)
qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
} else if (env->pmp_state.pmp[pmp_index].cfg_reg != val) {
env->pmp_state.pmp[pmp_index].cfg_reg = val;
- pmp_update_rule(env, pmp_index);
+ pmp_update_rule_addr(env, pmp_index);
return true;
}
} else {
@@ -207,6 +207,8 @@ void pmp_update_rule_nums(CPURISCVState *env)
env->pmp_state.num_rules++;
}
}
+
+ tlb_flush(env_cpu(env));
}
/*
@@ -492,7 +494,7 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t
reg_index,
/* If PMP permission of any addr has been changed, flush TLB pages. */
if (modified) {
- tlb_flush(env_cpu(env));
+ pmp_update_rule_nums(env);
}
}
@@ -545,7 +547,6 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t
addr_index,
if (env->pmp_state.pmp[addr_index].addr_reg != val) {
env->pmp_state.pmp[addr_index].addr_reg = val;
pmp_update_rule(env, addr_index);
- tlb_flush(env_cpu(env));
}
} else {
qemu_log_mask(LOG_GUEST_ERROR,
--
2.25.1
- [PATCH v4 0/7] target/riscv: Fix PMP related problem, Weiwei Li, 2023/04/22
- [PATCH v4 3/7] target/riscv: Flush TLB when pmpaddr is updated, Weiwei Li, 2023/04/22
- [PATCH v4 2/7] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp, Weiwei Li, 2023/04/22
- [PATCH v4 4/7] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes, Weiwei Li, 2023/04/22
- [PATCH v4 5/7] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1, Weiwei Li, 2023/04/22
- [PATCH v4 1/7] target/riscv: Update pmp_get_tlb_size(), Weiwei Li, 2023/04/22
- [PATCH v4 7/7] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write,
Weiwei Li <=
- [PATCH v4 6/7] target/riscv: Make the short cut really work in pmp_hart_has_privs, Weiwei Li, 2023/04/22