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[PATCH v4 3/7] target/riscv: Flush TLB when pmpaddr is updated
From: |
Weiwei Li |
Subject: |
[PATCH v4 3/7] target/riscv: Flush TLB when pmpaddr is updated |
Date: |
Sat, 22 Apr 2023 21:03:25 +0800 |
TLB should be flushed not only for pmpcfg csr changes, but also for
pmpaddr csr changes.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/pmp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index ad20a319c1..9ae3bfea22 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -537,6 +537,7 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t
addr_index,
if (!pmp_is_locked(env, addr_index)) {
env->pmp_state.pmp[addr_index].addr_reg = val;
pmp_update_rule(env, addr_index);
+ tlb_flush(env_cpu(env));
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpaddr write - locked\n");
--
2.25.1
- [PATCH v4 0/7] target/riscv: Fix PMP related problem, Weiwei Li, 2023/04/22
- [PATCH v4 3/7] target/riscv: Flush TLB when pmpaddr is updated,
Weiwei Li <=
- [PATCH v4 2/7] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp, Weiwei Li, 2023/04/22
- [PATCH v4 4/7] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes, Weiwei Li, 2023/04/22
- [PATCH v4 5/7] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1, Weiwei Li, 2023/04/22
- [PATCH v4 1/7] target/riscv: Update pmp_get_tlb_size(), Weiwei Li, 2023/04/22
- [PATCH v4 7/7] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write, Weiwei Li, 2023/04/22
- [PATCH v4 6/7] target/riscv: Make the short cut really work in pmp_hart_has_privs, Weiwei Li, 2023/04/22