Re: [PATCH v3 3/3] target/riscv: add TYPE_RISCV_DYNAMIC_CPU

[Alistair Francis]

On Wed, Apr 12, 2023 at 4:36 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> This new abstract type will be used to differentiate between static and
> non-static CPUs in query-cpu-definitions.
>
> All generic CPUs were changed to be of this type. Named CPUs are kept as
> TYPE_RISCV_CPU and will still be considered static.
>
> This is the output of query-cpu-definitions after this change for the
> riscv64 target:
>
> $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio
> {"QMP": {"version": (...)}
> {"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}}
> {"return": {}}
> {"execute": "query-cpu-definitions"}
> {"return": [
> {"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated": 
> false},
> {"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": true, 
> "deprecated": false},
> {"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated": 
> false},
> {"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, 
> "deprecated": false},
> {"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": true, 
> "deprecated": false},
> {"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": true, 
> "deprecated": false},
> {"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": true, 
> "deprecated": false}
> ]}
>
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu-qom.h        |  2 +-
>  target/riscv/cpu.c            | 20 ++++++++++++++++----
>  target/riscv/riscv-qmp-cmds.c |  4 ++++
>  3 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index b9318e0783..b29090ad86 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -23,6 +23,7 @@
>  #include "qom/object.h"
>
>  #define TYPE_RISCV_CPU "riscv-cpu"
> +#define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu"
>
>  #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
>  #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
> @@ -66,5 +67,4 @@ struct RISCVCPUClass {
>      DeviceRealize parent_realize;
>      ResettablePhases parent_phases;
>  };
> -
>  #endif /* RISCV_CPU_QOM_H */
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index fab38859ec..56f2b345cf 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1788,6 +1788,13 @@ void riscv_cpu_list(void)
>          .instance_init = initfn            \
>      }
>
> +#define DEFINE_DYNAMIC_CPU(type_name, initfn) \
> +    {                                         \
> +        .name = type_name,                    \
> +        .parent = TYPE_RISCV_DYNAMIC_CPU,     \
> +        .instance_init = initfn               \
> +    }
> +
>  static const TypeInfo riscv_cpu_type_infos[] = {
>      {
>          .name = TYPE_RISCV_CPU,
> @@ -1799,23 +1806,28 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>          .class_size = sizeof(RISCVCPUClass),
>          .class_init = riscv_cpu_class_init,
>      },
> -    DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
> +    {
> +        .name = TYPE_RISCV_DYNAMIC_CPU,
> +        .parent = TYPE_RISCV_CPU,
> +        .abstract = true,
> +    },
> +    DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY,      riscv_any_cpu_init),
>  #if defined(CONFIG_KVM)
>      DEFINE_CPU(TYPE_RISCV_CPU_HOST,             riscv_host_cpu_init),
>  #endif
>  #if defined(TARGET_RISCV32)
> -    DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           rv32_base_cpu_init),
> +    DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32,   rv32_base_cpu_init),
>      DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
>      DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32_sifive_e_cpu_init),
>      DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32_imafcu_nommu_cpu_init),
>      DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32_sifive_u_cpu_init),
>  #elif defined(TARGET_RISCV64)
> -    DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           rv64_base_cpu_init),
> +    DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64,   rv64_base_cpu_init),
>      DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64_sifive_e_cpu_init),
>      DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64_sifive_u_cpu_init),
>      DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C,         rv64_sifive_u_cpu_init),
>      DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906,       rv64_thead_c906_cpu_init),
> -    DEFINE_CPU(TYPE_RISCV_CPU_BASE128,          rv128_base_cpu_init),
> +    DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128,  rv128_base_cpu_init),
>  #endif
>  };
>
> diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c
> index 128677add9..5ecff1afb3 100644
> --- a/target/riscv/riscv-qmp-cmds.c
> +++ b/target/riscv/riscv-qmp-cmds.c
> @@ -33,11 +33,15 @@ static void riscv_cpu_add_definition(gpointer data, 
> gpointer user_data)
>      CpuDefinitionInfoList **cpu_list = user_data;
>      CpuDefinitionInfo *info = g_malloc0(sizeof(*info));
>      const char *typename = object_class_get_name(oc);
> +    ObjectClass *dyn_class;
>
>      info->name = g_strndup(typename,
>                             strlen(typename) - strlen("-" TYPE_RISCV_CPU));
>      info->q_typename = g_strdup(typename);
>
> +    dyn_class = object_class_dynamic_cast(oc, TYPE_RISCV_DYNAMIC_CPU);
> +    info->q_static = dyn_class == NULL;
> +
>      QAPI_LIST_PREPEND(*cpu_list, info);
>  }
>
> --
> 2.39.2
>
>