Re: [PATCH v3 1/3] target/riscv: add CPU QOM header

[Alistair Francis]

On Wed, Apr 12, 2023 at 4:36 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> QMP CPU commands are usually implemented by a separated file,
> <arch>-qmp-cmds.c, to allow them to be build only for softmmu targets.
> This file uses a CPU QOM header with basic QOM declarations for the
> arch.
>
> We'll introduce query-cpu-definitions for RISC-V CPUs in the next patch,
> but first we need a cpu-qom.h header with the definitions of
> TYPE_RISCV_CPU and RISCVCPUClass declarations. These were moved from
> cpu.h to the new file, and cpu.h now includes "cpu-qom.h".
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu-qom.h | 70 ++++++++++++++++++++++++++++++++++++++++++
>  target/riscv/cpu.h     | 46 +--------------------------
>  2 files changed, 71 insertions(+), 45 deletions(-)
>  create mode 100644 target/riscv/cpu-qom.h
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> new file mode 100644
> index 0000000000..b9318e0783
> --- /dev/null
> +++ b/target/riscv/cpu-qom.h
> @@ -0,0 +1,70 @@
> +/*
> + * QEMU RISC-V CPU QOM header
> + *
> + * Copyright (c) 2023 Ventana Micro Systems Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along 
> with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef RISCV_CPU_QOM_H
> +#define RISCV_CPU_QOM_H
> +
> +#include "hw/core/cpu.h"
> +#include "qom/object.h"
> +
> +#define TYPE_RISCV_CPU "riscv-cpu"
> +
> +#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
> +#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
> +#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
> +
> +#define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
> +#define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
> +#define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
> +#define TYPE_RISCV_CPU_BASE128          RISCV_CPU_TYPE_NAME("x-rv128")
> +#define TYPE_RISCV_CPU_IBEX             RISCV_CPU_TYPE_NAME("lowrisc-ibex")
> +#define TYPE_RISCV_CPU_SHAKTI_C         RISCV_CPU_TYPE_NAME("shakti-c")
> +#define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
> +#define TYPE_RISCV_CPU_SIFIVE_E34       RISCV_CPU_TYPE_NAME("sifive-e34")
> +#define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
> +#define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
> +#define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
> +#define TYPE_RISCV_CPU_THEAD_C906       RISCV_CPU_TYPE_NAME("thead-c906")
> +#define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
> +
> +#if defined(TARGET_RISCV32)
> +# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
> +#elif defined(TARGET_RISCV64)
> +# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
> +#endif
> +
> +typedef struct CPUArchState CPURISCVState;
> +
> +OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
> +
> +/**
> + * RISCVCPUClass:
> + * @parent_realize: The parent class' realize handler.
> + * @parent_phases: The parent class' reset phase handlers.
> + *
> + * A RISCV CPU model.
> + */
> +struct RISCVCPUClass {
> +    /*< private >*/
> +    CPUClass parent_class;
> +    /*< public >*/
> +    DeviceRealize parent_realize;
> +    ResettablePhases parent_phases;
> +};
> +
> +#endif /* RISCV_CPU_QOM_H */
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 86e08d10da..fa2655306d 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -28,6 +28,7 @@
>  #include "qemu/int128.h"
>  #include "cpu_bits.h"
>  #include "qapi/qapi-types-common.h"
> +#include "cpu-qom.h"
>
>  #define TCG_GUEST_DEFAULT_MO 0
>
> @@ -37,32 +38,6 @@
>   */
>  #define TARGET_INSN_START_EXTRA_WORDS 1
>
> -#define TYPE_RISCV_CPU "riscv-cpu"
> -
> -#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
> -#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
> -#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
> -
> -#define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
> -#define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
> -#define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
> -#define TYPE_RISCV_CPU_BASE128          RISCV_CPU_TYPE_NAME("x-rv128")
> -#define TYPE_RISCV_CPU_IBEX             RISCV_CPU_TYPE_NAME("lowrisc-ibex")
> -#define TYPE_RISCV_CPU_SHAKTI_C         RISCV_CPU_TYPE_NAME("shakti-c")
> -#define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
> -#define TYPE_RISCV_CPU_SIFIVE_E34       RISCV_CPU_TYPE_NAME("sifive-e34")
> -#define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
> -#define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
> -#define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
> -#define TYPE_RISCV_CPU_THEAD_C906       RISCV_CPU_TYPE_NAME("thead-c906")
> -#define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
> -
> -#if defined(TARGET_RISCV32)
> -# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
> -#elif defined(TARGET_RISCV64)
> -# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
> -#endif
> -
>  #define RV(x) ((target_ulong)1 << (x - 'A'))
>
>  /* Consider updating misa_ext_cfgs[] when adding new MISA bits here */
> @@ -101,8 +76,6 @@ enum {
>
>  #define MAX_RISCV_PMPS (16)
>
> -typedef struct CPUArchState CPURISCVState;
> -
>  #if !defined(CONFIG_USER_ONLY)
>  #include "pmp.h"
>  #include "debug.h"
> @@ -387,23 +360,6 @@ struct CPUArchState {
>      uint64_t kvm_timer_frequency;
>  };
>
> -OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
> -
> -/*
> - * RISCVCPUClass:
> - * @parent_realize: The parent class' realize handler.
> - * @parent_phases: The parent class' reset phase handlers.
> - *
> - * A RISCV CPU model.
> - */
> -struct RISCVCPUClass {
> -    /* < private > */
> -    CPUClass parent_class;
> -    /* < public > */
> -    DeviceRealize parent_realize;
> -    ResettablePhases parent_phases;
> -};
> -
>  /*
>   * map is a 16-bit bitmap: the most significant set bit in map is the maximum
>   * satp mode that is supported. It may be chosen by the user and must respect
> --
> 2.39.2
>
>