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[PATCH v3 11/25] target/arm: Adjust the order of Phys and Stage2 ARMMMUI
From: |
Richard Henderson |
Subject: |
[PATCH v3 11/25] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx |
Date: |
Tue, 21 Feb 2023 16:33:22 -1000 |
It will be helpful to have ARMMMUIdx_Phys_* to be in the same
relative order as ARMSecuritySpace enumerators. This requires
the adjustment to the nstable check. While there, check for being
in secure state rather than rely on clearing the low bit making
no change to non-secure state.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 12 ++++++------
target/arm/ptw.c | 12 +++++-------
2 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 203a3e0046..c5fc475cf8 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2855,18 +2855,18 @@ typedef enum ARMMMUIdx {
ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A,
ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A,
- /* TLBs with 1-1 mapping to the physical address spaces. */
- ARMMMUIdx_Phys_NS = 8 | ARM_MMU_IDX_A,
- ARMMMUIdx_Phys_S = 9 | ARM_MMU_IDX_A,
-
/*
* Used for second stage of an S12 page table walk, or for descriptor
* loads during first stage of an S1 page table walk. Note that both
* are in use simultaneously for SecureEL2: the security state for
* the S2 ptw is selected by the NS bit from the S1 ptw.
*/
- ARMMMUIdx_Stage2 = 10 | ARM_MMU_IDX_A,
- ARMMMUIdx_Stage2_S = 11 | ARM_MMU_IDX_A,
+ ARMMMUIdx_Stage2_S = 8 | ARM_MMU_IDX_A,
+ ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A,
+
+ /* TLBs with 1-1 mapping to the physical address spaces. */
+ ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A,
+ ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A,
/*
* These are not allocated TLBs and are used only for AT system
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 6fb72fb086..5ed5bb5039 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1410,16 +1410,14 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
descaddr |= (address >> (stride * (4 - level))) & indexmask;
descaddr &= ~7ULL;
nstable = extract32(tableattrs, 4, 1);
- if (nstable) {
+ if (nstable && ptw->in_secure) {
/*
* Stage2_S -> Stage2 or Phys_S -> Phys_NS
- * Assert that the non-secure idx are even, and relative order.
+ * Assert the relative order of the secure/non-secure indexes.
*/
- QEMU_BUILD_BUG_ON((ARMMMUIdx_Phys_NS & 1) != 0);
- QEMU_BUILD_BUG_ON((ARMMMUIdx_Stage2 & 1) != 0);
- QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS + 1 != ARMMMUIdx_Phys_S);
- QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2 + 1 != ARMMMUIdx_Stage2_S);
- ptw->in_ptw_idx &= ~1;
+ QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_S + 1 != ARMMMUIdx_Phys_NS);
+ QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 != ARMMMUIdx_Stage2);
+ ptw->in_ptw_idx += 1;
ptw->in_secure = false;
}
if (!S1_ptw_translate(env, ptw, descaddr, fi)) {
--
2.34.1
- Re: [PATCH v3 07/25] target/arm: SCR_EL3.NS may be RES1, (continued)
- [PATCH v3 13/25] target/arm: Remove __attribute__((nonnull)) from ptw.c, Richard Henderson, 2023/02/21
- [PATCH v3 05/25] target/arm: Add isar_feature_aa64_rme, Richard Henderson, 2023/02/21
- [PATCH v3 06/25] target/arm: Update SCR and HCR for RME, Richard Henderson, 2023/02/21
- [PATCH v3 09/25] target/arm: Introduce ARMSecuritySpace, Richard Henderson, 2023/02/21
- [PATCH v3 12/25] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root}, Richard Henderson, 2023/02/21
- [PATCH v3 11/25] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx,
Richard Henderson <=
- [PATCH v3 14/25] target/arm: Pipe ARMSecuritySpace through ptw.c, Richard Henderson, 2023/02/21
- [PATCH v3 22/25] target/arm: Implement GPC exceptions, Richard Henderson, 2023/02/21
- [PATCH v3 15/25] target/arm: NSTable is RES0 for the RME EL3 regime, Richard Henderson, 2023/02/21
- [PATCH v3 19/25] target/arm: Move s1_is_el0 into S1Translate, Richard Henderson, 2023/02/21
- [PATCH v3 16/25] target/arm: Handle Block and Page bits for security space, Richard Henderson, 2023/02/21
- [PATCH v3 18/25] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate, Richard Henderson, 2023/02/21
- [PATCH v3 17/25] target/arm: Handle no-execute for Realm and Root regimes, Richard Henderson, 2023/02/21