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[PATCH v3 06/25] target/arm: Update SCR and HCR for RME
From: |
Richard Henderson |
Subject: |
[PATCH v3 06/25] target/arm: Update SCR and HCR for RME |
Date: |
Tue, 21 Feb 2023 16:33:17 -1000 |
Define the missing SCR and HCR bits, allow SCR_NSE and {SCR,HCR}_GPF
to be set, and invalidate TLBs when NSE changes.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 5 +++--
target/arm/helper.c | 10 ++++++++--
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index b046f96e4e..230241cf93 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1650,7 +1650,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t
val, uint32_t mask)
#define HCR_TERR (1ULL << 36)
#define HCR_TEA (1ULL << 37)
#define HCR_MIOCNCE (1ULL << 38)
-/* RES0 bit 39 */
+#define HCR_TME (1ULL << 39)
#define HCR_APK (1ULL << 40)
#define HCR_API (1ULL << 41)
#define HCR_NV (1ULL << 42)
@@ -1659,7 +1659,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t
val, uint32_t mask)
#define HCR_NV2 (1ULL << 45)
#define HCR_FWB (1ULL << 46)
#define HCR_FIEN (1ULL << 47)
-/* RES0 bit 48 */
+#define HCR_GPF (1ULL << 48)
#define HCR_TID4 (1ULL << 49)
#define HCR_TICAB (1ULL << 50)
#define HCR_AMVOFFEN (1ULL << 51)
@@ -1724,6 +1724,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t
val, uint32_t mask)
#define SCR_TRNDR (1ULL << 40)
#define SCR_ENTP2 (1ULL << 41)
#define SCR_GPF (1ULL << 48)
+#define SCR_NSE (1ULL << 62)
#define HSTR_TTEE (1 << 16)
#define HSTR_TJDBX (1 << 17)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 37d9267fb4..3650234c73 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1875,6 +1875,9 @@ static void scr_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
if (cpu_isar_feature(aa64_fgt, cpu)) {
valid_mask |= SCR_FGTEN;
}
+ if (cpu_isar_feature(aa64_rme, cpu)) {
+ valid_mask |= SCR_NSE | SCR_GPF;
+ }
} else {
valid_mask &= ~(SCR_RW | SCR_ST);
if (cpu_isar_feature(aa32_ras, cpu)) {
@@ -1904,10 +1907,10 @@ static void scr_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
env->cp15.scr_el3 = value;
/*
- * If SCR_EL3.NS changes, i.e. arm_is_secure_below_el3, then
+ * If SCR_EL3.{NS,NSE} changes, i.e. change of security state,
* we must invalidate all TLBs below EL3.
*/
- if (changed & SCR_NS) {
+ if (changed & (SCR_NS | SCR_NSE)) {
tlb_flush_by_mmuidx(env_cpu(env), (ARMMMUIdxBit_E10_0 |
ARMMMUIdxBit_E20_0 |
ARMMMUIdxBit_E10_1 |
@@ -5655,6 +5658,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t
value, uint64_t valid_mask)
if (cpu_isar_feature(aa64_fwb, cpu)) {
valid_mask |= HCR_FWB;
}
+ if (cpu_isar_feature(aa64_rme, cpu)) {
+ valid_mask |= HCR_GPF;
+ }
}
if (cpu_isar_feature(any_evt, cpu)) {
--
2.34.1
- Re: [PATCH v3 04/25] target/arm: Rewrite check_s2_mmu_setup, (continued)
- [PATCH v3 10/25] include/exec/memattrs: Add two bits of space to MemTxAttrs, Richard Henderson, 2023/02/21
- [PATCH v3 08/25] target/arm: Add RME cpregs, Richard Henderson, 2023/02/21
- [PATCH v3 07/25] target/arm: SCR_EL3.NS may be RES1, Richard Henderson, 2023/02/21
- [PATCH v3 13/25] target/arm: Remove __attribute__((nonnull)) from ptw.c, Richard Henderson, 2023/02/21
- [PATCH v3 05/25] target/arm: Add isar_feature_aa64_rme, Richard Henderson, 2023/02/21
- [PATCH v3 06/25] target/arm: Update SCR and HCR for RME,
Richard Henderson <=
- [PATCH v3 09/25] target/arm: Introduce ARMSecuritySpace, Richard Henderson, 2023/02/21
- [PATCH v3 12/25] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root}, Richard Henderson, 2023/02/21
- [PATCH v3 11/25] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx, Richard Henderson, 2023/02/21
- [PATCH v3 14/25] target/arm: Pipe ARMSecuritySpace through ptw.c, Richard Henderson, 2023/02/21
- [PATCH v3 22/25] target/arm: Implement GPC exceptions, Richard Henderson, 2023/02/21
- [PATCH v3 15/25] target/arm: NSTable is RES0 for the RME EL3 regime, Richard Henderson, 2023/02/21
- [PATCH v3 19/25] target/arm: Move s1_is_el0 into S1Translate, Richard Henderson, 2023/02/21