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[PATCH v3 05/25] target/arm: Add isar_feature_aa64_rme
From: |
Richard Henderson |
Subject: |
[PATCH v3 05/25] target/arm: Add isar_feature_aa64_rme |
Date: |
Tue, 21 Feb 2023 16:33:16 -1000 |
Add the missing field for ID_AA64PFR0, and the predicate.
Disable it if EL3 is forced off by the board or command-line.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 6 ++++++
target/arm/cpu.c | 4 ++++
2 files changed, 10 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index cb4e405f04..b046f96e4e 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2190,6 +2190,7 @@ FIELD(ID_AA64PFR0, SEL2, 36, 4)
FIELD(ID_AA64PFR0, MPAM, 40, 4)
FIELD(ID_AA64PFR0, AMU, 44, 4)
FIELD(ID_AA64PFR0, DIT, 48, 4)
+FIELD(ID_AA64PFR0, RME, 52, 4)
FIELD(ID_AA64PFR0, CSV2, 56, 4)
FIELD(ID_AA64PFR0, CSV3, 60, 4)
@@ -3808,6 +3809,11 @@ static inline bool isar_feature_aa64_sel2(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0;
}
+static inline bool isar_feature_aa64_rme(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0;
+}
+
static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 876ab8f3bf..83685ed247 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1947,6 +1947,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
ID_AA64PFR0, EL3, 0);
+
+ /* Disable the realm management extension, which requires EL3. */
+ cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
+ ID_AA64PFR0, RME, 0);
}
if (!cpu->has_el2) {
--
2.34.1
- Re: [PATCH v3 01/25] target/arm: Handle m-profile in arm_is_secure, (continued)
- [PATCH v3 04/25] target/arm: Rewrite check_s2_mmu_setup, Richard Henderson, 2023/02/21
- [PATCH v3 10/25] include/exec/memattrs: Add two bits of space to MemTxAttrs, Richard Henderson, 2023/02/21
- [PATCH v3 08/25] target/arm: Add RME cpregs, Richard Henderson, 2023/02/21
- [PATCH v3 07/25] target/arm: SCR_EL3.NS may be RES1, Richard Henderson, 2023/02/21
- [PATCH v3 13/25] target/arm: Remove __attribute__((nonnull)) from ptw.c, Richard Henderson, 2023/02/21
- [PATCH v3 05/25] target/arm: Add isar_feature_aa64_rme,
Richard Henderson <=
- [PATCH v3 06/25] target/arm: Update SCR and HCR for RME, Richard Henderson, 2023/02/21
- [PATCH v3 09/25] target/arm: Introduce ARMSecuritySpace, Richard Henderson, 2023/02/21
- [PATCH v3 12/25] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root}, Richard Henderson, 2023/02/21
- [PATCH v3 11/25] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx, Richard Henderson, 2023/02/21
- [PATCH v3 14/25] target/arm: Pipe ARMSecuritySpace through ptw.c, Richard Henderson, 2023/02/21
- [PATCH v3 22/25] target/arm: Implement GPC exceptions, Richard Henderson, 2023/02/21
- [PATCH v3 15/25] target/arm: NSTable is RES0 for the RME EL3 regime, Richard Henderson, 2023/02/21