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Re: [PATCH v5 6/8] hw/cxl: Fix endian issues in CXL RAS capability defau


From: Philippe Mathieu-Daudé
Subject: Re: [PATCH v5 6/8] hw/cxl: Fix endian issues in CXL RAS capability defaults / masks
Date: Tue, 21 Feb 2023 23:06:33 +0100
User-agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.8.0

On 21/2/23 16:21, Jonathan Cameron wrote:
As these are about to be modified, fix the endian handle for
this set of registers rather than making it worse.

Note that CXL is currently only supported in QEMU on
x86 (arm64 patches out of tree) so we aren't going to yet hit
an problems with big endian. However it is good to avoid making
things worse for that support in the future.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
  hw/cxl/cxl-component-utils.c | 18 +++++++++---------
  1 file changed, 9 insertions(+), 9 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>




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