[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 20/30] hw/arm/smmu-common: Fix TTB1 handling
From: |
Peter Maydell |
Subject: |
[PULL 20/30] hw/arm/smmu-common: Fix TTB1 handling |
Date: |
Thu, 16 Feb 2023 17:11:13 +0000 |
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
Addresses targeting the second translation table (TTB1) in the SMMU have
all upper bits set (except for the top byte when TBI is enabled). Fix
the TTB1 check.
Reported-by: Ola Hugosson <ola.hugosson@arm.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230214171921.1917916-3-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/smmu-common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index 2b8c67b9a1d..0a5a60ca1e9 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -249,7 +249,7 @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t
iova)
/* there is a ttbr0 region and we are in it (high bits all zero) */
return &cfg->tt[0];
} else if (cfg->tt[1].tsz &&
- !extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) {
+ sextract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte) ==
-1) {
/* there is a ttbr1 region and we are in it (high bits all one) */
return &cfg->tt[1];
} else if (!cfg->tt[0].tsz) {
--
2.34.1
- [PULL 10/30] target/arm: Store CPUARMState::nvic as NVICState*, (continued)
- [PULL 10/30] target/arm: Store CPUARMState::nvic as NVICState*, Peter Maydell, 2023/02/16
- [PULL 11/30] target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h', Peter Maydell, 2023/02/16
- [PULL 14/30] hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency, Peter Maydell, 2023/02/16
- [PULL 12/30] tests/avocado: retire the Aarch64 TCG tests from boot_linux.py, Peter Maydell, 2023/02/16
- [PULL 15/30] arm/virt: don't try to spell out the accelerator, Peter Maydell, 2023/02/16
- [PULL 13/30] hw/arm/smmuv3: Add GBPA register, Peter Maydell, 2023/02/16
- [PULL 16/30] MAINTAINERS: Add myself to maintainers and remove Havard, Peter Maydell, 2023/02/16
- [PULL 18/30] hw/arm: Attach PSPI module to NPCM7XX SoC, Peter Maydell, 2023/02/16
- [PULL 17/30] hw/ssi: Add Nuvoton PSPI Module, Peter Maydell, 2023/02/16
- [PULL 19/30] hw/arm/smmu-common: Support 64-bit addresses, Peter Maydell, 2023/02/16
- [PULL 20/30] hw/arm/smmu-common: Fix TTB1 handling,
Peter Maydell <=
- [PULL 21/30] target/arm: rename handle_semihosting to tcg_handle_semihosting, Peter Maydell, 2023/02/16
- [PULL 22/30] target/arm: wrap psci call with tcg_enabled, Peter Maydell, 2023/02/16
- [PULL 23/30] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled(), Peter Maydell, 2023/02/16
- [PULL 25/30] target/arm: Move cpregs code out of cpu.h, Peter Maydell, 2023/02/16
- [PULL 26/30] tests/avocado: Skip tests that require a missing accelerator, Peter Maydell, 2023/02/16
- [PULL 28/30] target/arm: Use "max" as default cpu for the virt machine with KVM, Peter Maydell, 2023/02/16
- [PULL 24/30] target/arm: Move PC alignment check, Peter Maydell, 2023/02/16
- [PULL 27/30] tests/avocado: Tag TCG tests with accel:tcg, Peter Maydell, 2023/02/16
- [PULL 29/30] tests/qtest: arm-cpu-features: Match tests to required accelerators, Peter Maydell, 2023/02/16
- [PULL 30/30] tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG, Peter Maydell, 2023/02/16