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[PULL 13/30] hw/arm/smmuv3: Add GBPA register
From: |
Peter Maydell |
Subject: |
[PULL 13/30] hw/arm/smmuv3: Add GBPA register |
Date: |
Thu, 16 Feb 2023 17:11:06 +0000 |
From: Mostafa Saleh <smostafa@google.com>
GBPA register can be used to globally abort all
transactions.
It is described in the SMMU manual in "6.3.14 SMMU_GBPA".
ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to
be zero(Do not abort incoming transactions).
Other fields have default values of Use Incoming.
If UPDATE is not set, the write is ignored. This is the only permitted
behavior in SMMUv3.2 and later.(6.3.14.1 Update procedure)
As this patch adds a new state to the SMMU (GBPA), it is added
in a new subsection for forward migration compatibility.
GBPA is only migrated if its value is different from the reset value.
It does this to be backward migration compatible if SW didn't write
the register.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20230214094009.2445653-1-smostafa@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/smmuv3-internal.h | 7 +++++++
include/hw/arm/smmuv3.h | 1 +
hw/arm/smmuv3.c | 43 +++++++++++++++++++++++++++++++++++++++-
3 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index bce161870f6..e8f0ebf25e3 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -79,6 +79,13 @@ REG32(CR0ACK, 0x24)
REG32(CR1, 0x28)
REG32(CR2, 0x2c)
REG32(STATUSR, 0x40)
+REG32(GBPA, 0x44)
+ FIELD(GBPA, ABORT, 20, 1)
+ FIELD(GBPA, UPDATE, 31, 1)
+
+/* Use incoming. */
+#define SMMU_GBPA_RESET_VAL 0x1000
+
REG32(IRQ_CTRL, 0x50)
FIELD(IRQ_CTRL, GERROR_IRQEN, 0, 1)
FIELD(IRQ_CTRL, PRI_IRQEN, 1, 1)
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
index b6dd0875264..a0c026402e1 100644
--- a/include/hw/arm/smmuv3.h
+++ b/include/hw/arm/smmuv3.h
@@ -45,6 +45,7 @@ struct SMMUv3State {
uint32_t cr[3];
uint32_t cr0ack;
uint32_t statusr;
+ uint32_t gbpa;
uint32_t irq_ctrl;
uint32_t gerror;
uint32_t gerrorn;
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 955b89c8d59..270c80b665f 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -285,6 +285,7 @@ static void smmuv3_init_regs(SMMUv3State *s)
s->gerror = 0;
s->gerrorn = 0;
s->statusr = 0;
+ s->gbpa = SMMU_GBPA_RESET_VAL;
}
static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
@@ -659,7 +660,11 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion
*mr, hwaddr addr,
qemu_mutex_lock(&s->mutex);
if (!smmu_enabled(s)) {
- status = SMMU_TRANS_DISABLE;
+ if (FIELD_EX32(s->gbpa, GBPA, ABORT)) {
+ status = SMMU_TRANS_ABORT;
+ } else {
+ status = SMMU_TRANS_DISABLE;
+ }
goto epilogue;
}
@@ -1170,6 +1175,16 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr
offset,
case A_GERROR_IRQ_CFG2:
s->gerror_irq_cfg2 = data;
return MEMTX_OK;
+ case A_GBPA:
+ /*
+ * If UPDATE is not set, the write is ignored. This is the only
+ * permitted behavior in SMMUv3.2 and later.
+ */
+ if (data & R_GBPA_UPDATE_MASK) {
+ /* Ignore update bit as write is synchronous. */
+ s->gbpa = data & ~R_GBPA_UPDATE_MASK;
+ }
+ return MEMTX_OK;
case A_STRTAB_BASE: /* 64b */
s->strtab_base = deposit64(s->strtab_base, 0, 32, data);
return MEMTX_OK;
@@ -1318,6 +1333,9 @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr
offset,
case A_STATUSR:
*data = s->statusr;
return MEMTX_OK;
+ case A_GBPA:
+ *data = s->gbpa;
+ return MEMTX_OK;
case A_IRQ_CTRL:
case A_IRQ_CTRL_ACK:
*data = s->irq_ctrl;
@@ -1482,6 +1500,25 @@ static const VMStateDescription vmstate_smmuv3_queue = {
},
};
+static bool smmuv3_gbpa_needed(void *opaque)
+{
+ SMMUv3State *s = opaque;
+
+ /* Only migrate GBPA if it has different reset value. */
+ return s->gbpa != SMMU_GBPA_RESET_VAL;
+}
+
+static const VMStateDescription vmstate_gbpa = {
+ .name = "smmuv3/gbpa",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = smmuv3_gbpa_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(gbpa, SMMUv3State),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static const VMStateDescription vmstate_smmuv3 = {
.name = "smmuv3",
.version_id = 1,
@@ -1512,6 +1549,10 @@ static const VMStateDescription vmstate_smmuv3 = {
VMSTATE_END_OF_LIST(),
},
+ .subsections = (const VMStateDescription * []) {
+ &vmstate_gbpa,
+ NULL
+ }
};
static void smmuv3_instance_init(Object *obj)
--
2.34.1
- [PULL 06/30] target/arm: Avoid resetting CPUARMState::eabi field, (continued)
- [PULL 06/30] target/arm: Avoid resetting CPUARMState::eabi field, Peter Maydell, 2023/02/16
- [PULL 07/30] target/arm: Restrict CPUARMState::gicv3state to sysemu, Peter Maydell, 2023/02/16
- [PULL 05/30] target/arm: Convert CPUARMState::eabi to boolean, Peter Maydell, 2023/02/16
- [PULL 08/30] target/arm: Restrict CPUARMState::arm_boot_info to sysemu, Peter Maydell, 2023/02/16
- [PULL 09/30] target/arm: Restrict CPUARMState::nvic to sysemu, Peter Maydell, 2023/02/16
- [PULL 10/30] target/arm: Store CPUARMState::nvic as NVICState*, Peter Maydell, 2023/02/16
- [PULL 11/30] target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h', Peter Maydell, 2023/02/16
- [PULL 14/30] hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency, Peter Maydell, 2023/02/16
- [PULL 12/30] tests/avocado: retire the Aarch64 TCG tests from boot_linux.py, Peter Maydell, 2023/02/16
- [PULL 15/30] arm/virt: don't try to spell out the accelerator, Peter Maydell, 2023/02/16
- [PULL 13/30] hw/arm/smmuv3: Add GBPA register,
Peter Maydell <=
- [PULL 16/30] MAINTAINERS: Add myself to maintainers and remove Havard, Peter Maydell, 2023/02/16
- [PULL 18/30] hw/arm: Attach PSPI module to NPCM7XX SoC, Peter Maydell, 2023/02/16
- [PULL 17/30] hw/ssi: Add Nuvoton PSPI Module, Peter Maydell, 2023/02/16
- [PULL 19/30] hw/arm/smmu-common: Support 64-bit addresses, Peter Maydell, 2023/02/16
- [PULL 20/30] hw/arm/smmu-common: Fix TTB1 handling, Peter Maydell, 2023/02/16
- [PULL 21/30] target/arm: rename handle_semihosting to tcg_handle_semihosting, Peter Maydell, 2023/02/16
- [PULL 22/30] target/arm: wrap psci call with tcg_enabled, Peter Maydell, 2023/02/16
- [PULL 23/30] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled(), Peter Maydell, 2023/02/16
- [PULL 25/30] target/arm: Move cpregs code out of cpu.h, Peter Maydell, 2023/02/16
- [PULL 26/30] tests/avocado: Skip tests that require a missing accelerator, Peter Maydell, 2023/02/16