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[PATCH RESEND v5 14/28] target/arm: Move regime_using_lpae_format into i
From: |
Fabiano Rosas |
Subject: |
[PATCH RESEND v5 14/28] target/arm: Move regime_using_lpae_format into internal.h |
Date: |
Mon, 13 Feb 2023 17:29:13 -0300 |
This function is needed by common code (ptw.c), so move it along with
the other regime_* functions in internal.h. When we enable the build
without TCG, the tlb_helper.c file will not be present.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/arm/internals.h | 21 ++++++++++++++++++---
target/arm/tcg/tlb_helper.c | 18 ------------------
2 files changed, 18 insertions(+), 21 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 880b97be0d..4aa3bf974e 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -614,9 +614,6 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState
*env,
/* Return the MMU index for a v7M CPU in the specified security state */
ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
-/* Return true if the translation regime is using LPAE format page tables */
-bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
-
/*
* Return true if the stage 1 translation regime is using LPAE
* format page tables
@@ -781,6 +778,24 @@ static inline uint64_t regime_tcr(CPUARMState *env,
ARMMMUIdx mmu_idx)
return env->cp15.tcr_el[regime_el(env, mmu_idx)];
}
+/* Return true if the translation regime is using LPAE format page tables */
+static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx
mmu_idx)
+{
+ int el = regime_el(env, mmu_idx);
+ if (el == 2 || arm_el_is_aa64(env, el)) {
+ return true;
+ }
+ if (arm_feature(env, ARM_FEATURE_PMSA) &&
+ arm_feature(env, ARM_FEATURE_V8)) {
+ return true;
+ }
+ if (arm_feature(env, ARM_FEATURE_LPAE)
+ && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
+ return true;
+ }
+ return false;
+}
+
/**
* arm_num_brps: Return number of implemented breakpoints.
* Note that the ID register BRPS field is "number of bps - 1",
diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c
index 60abcbebe6..31eb77f7df 100644
--- a/target/arm/tcg/tlb_helper.c
+++ b/target/arm/tcg/tlb_helper.c
@@ -12,24 +12,6 @@
#include "exec/helper-proto.h"
-/* Return true if the translation regime is using LPAE format page tables */
-bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
-{
- int el = regime_el(env, mmu_idx);
- if (el == 2 || arm_el_is_aa64(env, el)) {
- return true;
- }
- if (arm_feature(env, ARM_FEATURE_PMSA) &&
- arm_feature(env, ARM_FEATURE_V8)) {
- return true;
- }
- if (arm_feature(env, ARM_FEATURE_LPAE)
- && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
- return true;
- }
- return false;
-}
-
/*
* Returns true if the stage 1 translation regime is using LPAE format page
* tables. Used when raising alignment exceptions, whose FSR changes depending
--
2.35.3
- [PATCH RESEND v5 04/28] target/arm: Move PC alignment check, (continued)
- [PATCH RESEND v5 04/28] target/arm: Move PC alignment check, Fabiano Rosas, 2023/02/13
- [PATCH RESEND v5 06/28] target/arm: Move cpregs code into cpregs.c, Fabiano Rosas, 2023/02/13
- [PATCH RESEND v5 07/28] target/arm: Move define_debug_regs() to cpregs.c, Fabiano Rosas, 2023/02/13
- [PATCH RESEND v5 08/28] target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled, Fabiano Rosas, 2023/02/13
- [PATCH RESEND v5 09/28] target/arm: move translate modules to tcg/, Fabiano Rosas, 2023/02/13
- [PATCH RESEND v5 10/28] target/arm: move helpers to tcg/, Fabiano Rosas, 2023/02/13
- [PATCH RESEND v5 11/28] target/arm: Move psci.c into the tcg directory, Fabiano Rosas, 2023/02/13
- [PATCH RESEND v5 12/28] target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled, Fabiano Rosas, 2023/02/13
- [PATCH RESEND v5 13/28] target/arm: Move hflags code into the tcg directory, Fabiano Rosas, 2023/02/13
- [PATCH RESEND v5 14/28] target/arm: Move regime_using_lpae_format into internal.h,
Fabiano Rosas <=
- [PATCH RESEND v5 15/28] target/arm: Don't access TCG code when debugging with KVM, Fabiano Rosas, 2023/02/13
- [PATCH RESEND v5 16/28] cpu-defs.h: Expose CPUTLBEntryFull to non-TCG code, Fabiano Rosas, 2023/02/13
- [PATCH RESEND v5 17/28] target/arm: Move cortex sysregs into cpregs.c, Fabiano Rosas, 2023/02/13
- [PATCH RESEND v5 18/28] tests/avocado: Skip tests that require a missing accelerator, Fabiano Rosas, 2023/02/13
- [PATCH RESEND v5 19/28] tests/avocado: Tag TCG tests with accel:tcg, Fabiano Rosas, 2023/02/13
- [PATCH RESEND v5 20/28] target/arm: Move 64-bit TCG CPUs into tcg/, Fabiano Rosas, 2023/02/13
- [PATCH RESEND v5 21/28] target/arm: move cpu_tcg to tcg/cpu32.c, Fabiano Rosas, 2023/02/13
- [PATCH RESEND v5 22/28] target/arm: Use "max" as default cpu for the virt machine with KVM, Fabiano Rosas, 2023/02/13
- [PATCH RESEND v5 23/28] tests/qtest: arm-cpu-features: Match tests to required accelerators, Fabiano Rosas, 2023/02/13