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[PULL 19/32] RISC-V: Adding XTheadBs ISA extension
From: |
Alistair Francis |
Subject: |
[PULL 19/32] RISC-V: Adding XTheadBs ISA extension |
Date: |
Tue, 7 Feb 2023 17:09:30 +1000 |
From: Christoph Müllner <christoph.muellner@vrull.eu>
This patch adds support for the XTheadBs ISA extension.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-6-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/xthead.decode | 3 +++
target/riscv/cpu.c | 2 ++
target/riscv/translate.c | 3 ++-
target/riscv/insn_trans/trans_xthead.c.inc | 15 +++++++++++++++
5 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index be86c2fb95..876eaebd0e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -475,6 +475,7 @@ struct RISCVCPUConfig {
/* Vendor-specific custom extensions */
bool ext_xtheadba;
bool ext_xtheadbb;
+ bool ext_xtheadbs;
bool ext_xtheadcmo;
bool ext_xtheadsync;
bool ext_XVentanaCondOps;
diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
index 8cd140891b..8494805611 100644
--- a/target/riscv/xthead.decode
+++ b/target/riscv/xthead.decode
@@ -58,6 +58,9 @@ th_rev 1000001 00000 ..... 001 ..... 0001011 @r2
th_revw 1001000 00000 ..... 001 ..... 0001011 @r2
th_tstnbz 1000000 00000 ..... 001 ..... 0001011 @r2
+# XTheadBs
+th_tst 100010 ...... ..... 001 ..... 0001011 @sh6
+
# XTheadCmo
th_dcache_call 0000000 00001 00000 000 00000 0001011
th_dcache_ciall 0000000 00011 00000 000 00000 0001011
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index def27a53f2..c541924214 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -111,6 +111,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba),
ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb),
+ ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs),
ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0,
ext_XVentanaCondOps),
@@ -1094,6 +1095,7 @@ static Property riscv_cpu_extensions[] = {
/* Vendor-specific custom extensions */
DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
+ DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,
false),
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 387ef0ad8b..880324e617 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -133,7 +133,8 @@ static bool always_true_p(DisasContext *ctx
__attribute__((__unused__)))
static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__)))
{
return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
- ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync;
+ ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
+ ctx->cfg_ptr->ext_xtheadsync;
}
#define MATERIALISE_EXT_PREDICATE(ext) \
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc
b/target/riscv/insn_trans/trans_xthead.c.inc
index ebfab90dd9..bc1605445d 100644
--- a/target/riscv/insn_trans/trans_xthead.c.inc
+++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -28,6 +28,12 @@
} \
} while (0)
+#define REQUIRE_XTHEADBS(ctx) do { \
+ if (!ctx->cfg_ptr->ext_xtheadbs) { \
+ return false; \
+ } \
+} while (0)
+
#define REQUIRE_XTHEADCMO(ctx) do { \
if (!ctx->cfg_ptr->ext_xtheadcmo) { \
return false; \
@@ -191,6 +197,15 @@ static bool trans_th_tstnbz(DisasContext *ctx,
arg_th_tstnbz *a)
return gen_unary(ctx, a, EXT_ZERO, gen_th_tstnbz);
}
+/* XTheadBs */
+
+/* th.tst is an alternate encoding for bexti (from Zbs) */
+static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a)
+{
+ REQUIRE_XTHEADBS(ctx);
+ return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
+}
+
/* XTheadCmo */
static inline int priv_level(DisasContext *ctx)
--
2.39.1
- [PULL 11/32] target/riscv: set tval for triggered watchpoints, (continued)
- [PULL 11/32] target/riscv: set tval for triggered watchpoints, Alistair Francis, 2023/02/07
- [PULL 07/32] target/riscv: Ensure opcode is saved for all relevant instructions, Alistair Francis, 2023/02/07
- [PULL 12/32] hw/riscv/boot.c: calculate fdt size after fdt_pack(), Alistair Francis, 2023/02/07
- [PULL 09/32] hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms', Alistair Francis, 2023/02/07
- [PULL 13/32] hw/riscv: split fdt address calculation from fdt load, Alistair Francis, 2023/02/07
- [PULL 14/32] hw/riscv: change riscv_compute_fdt_addr() semantics, Alistair Francis, 2023/02/07
- [PULL 16/32] RISC-V: Adding XTheadSync ISA extension, Alistair Francis, 2023/02/07
- [PULL 15/32] RISC-V: Adding XTheadCmo ISA extension, Alistair Francis, 2023/02/07
- [PULL 17/32] RISC-V: Adding XTheadBa ISA extension, Alistair Francis, 2023/02/07
- [PULL 18/32] RISC-V: Adding XTheadBb ISA extension, Alistair Francis, 2023/02/07
- [PULL 19/32] RISC-V: Adding XTheadBs ISA extension,
Alistair Francis <=
- [PULL 20/32] RISC-V: Adding XTheadCondMov ISA extension, Alistair Francis, 2023/02/07
- [PULL 21/32] RISC-V: Adding T-Head multiply-accumulate instructions, Alistair Francis, 2023/02/07
- [PULL 22/32] RISC-V: Adding T-Head MemPair extension, Alistair Francis, 2023/02/07
- [PULL 23/32] RISC-V: Adding T-Head MemIdx extension, Alistair Francis, 2023/02/07
- [PULL 24/32] RISC-V: Adding T-Head FMemIdx extension, Alistair Francis, 2023/02/07
- [PULL 25/32] RISC-V: Set minimum priv version for Zfh to 1.11, Alistair Francis, 2023/02/07
- [PULL 26/32] RISC-V: Add initial support for T-Head C906, Alistair Francis, 2023/02/07
- [PULL 27/32] RISC-V: Adding XTheadFmv ISA extension, Alistair Francis, 2023/02/07
- [PULL 28/32] target/riscv: add a MAINTAINERS entry for XThead* extension support, Alistair Francis, 2023/02/07
- [PULL 31/32] target/riscv: fix SBI getchar handler for KVM, Alistair Francis, 2023/02/07