[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 23/33] target/arm: Mark up sysregs for HFGRTR bits 36..63
From: |
Peter Maydell |
Subject: |
[PULL 23/33] target/arm: Mark up sysregs for HFGRTR bits 36..63 |
Date: |
Fri, 3 Feb 2023 14:29:17 +0000 |
Mark up the sysreg definitions for the registers trapped
by HFGRTR/HFGWTR bits 36..63.
Of these, some correspond to RAS registers which we implement as
always-UNDEF: these don't need any extra handling for FGT because the
UNDEF-to-EL1 always takes priority over any theoretical
FGT-trap-to-EL2.
Bit 50 (NACCDATA_EL1) is for the ACCDATA_EL1 register which is part
of the FEAT_LS64_ACCDATA feature which we don't yet implement.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-14-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-14-peter.maydell@linaro.org
---
target/arm/cpregs.h | 7 +++++++
hw/intc/arm_gicv3_cpuif.c | 2 ++
target/arm/helper.c | 10 ++++++++++
3 files changed, 19 insertions(+)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 1b219242d5d..fef8ad08acc 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -615,6 +615,13 @@ typedef enum FGTBit {
DO_BIT(HFGRTR, TPIDR_EL1),
DO_BIT(HFGRTR, TPIDRRO_EL0),
DO_BIT(HFGRTR, TPIDR_EL0),
+ DO_BIT(HFGRTR, TTBR0_EL1),
+ DO_BIT(HFGRTR, TTBR1_EL1),
+ DO_BIT(HFGRTR, VBAR_EL1),
+ DO_BIT(HFGRTR, ICC_IGRPENN_EL1),
+ DO_BIT(HFGRTR, ERRIDR_EL1),
+ DO_REV_BIT(HFGRTR, NSMPRI_EL1),
+ DO_REV_BIT(HFGRTR, NTPIDR2_EL0),
} FGTBit;
#undef DO_BIT
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 9a7fc190994..d07b13eb270 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -2378,6 +2378,7 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 6,
.type = ARM_CP_IO | ARM_CP_NO_RAW,
.access = PL1_RW, .accessfn = gicv3_fiq_access,
+ .fgt = FGT_ICC_IGRPENN_EL1,
.readfn = icc_igrpen_read,
.writefn = icc_igrpen_write,
},
@@ -2386,6 +2387,7 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 7,
.type = ARM_CP_IO | ARM_CP_NO_RAW,
.access = PL1_RW, .accessfn = gicv3_irq_access,
+ .fgt = FGT_ICC_IGRPENN_EL1,
.readfn = icc_igrpen_read,
.writefn = icc_igrpen_write,
},
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9f6d9e2a3c9..a48b022def6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4158,12 +4158,14 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
{ .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
.access = PL1_RW, .accessfn = access_tvm_trvm,
+ .fgt = FGT_TTBR0_EL1,
.writefn = vmsa_ttbr_write, .resetvalue = 0,
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
offsetof(CPUARMState, cp15.ttbr0_ns) } },
{ .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
.access = PL1_RW, .accessfn = access_tvm_trvm,
+ .fgt = FGT_TTBR1_EL1,
.writefn = vmsa_ttbr_write, .resetvalue = 0,
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
offsetof(CPUARMState, cp15.ttbr1_ns) } },
@@ -6488,6 +6490,10 @@ static void disr_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t val)
* ERRSELR_EL1
* may generate UNDEFINED, which is the effect we get by not
* listing them at all.
+ *
+ * These registers have fine-grained trap bits, but UNDEF-to-EL1
+ * is higher priority than FGT-to-EL2 so we do not need to list them
+ * in order to check for an FGT.
*/
static const ARMCPRegInfo minimal_ras_reginfo[] = {
{ .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH,
@@ -6497,6 +6503,7 @@ static const ARMCPRegInfo minimal_ras_reginfo[] = {
{ .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
.access = PL1_R, .accessfn = access_terr,
+ .fgt = FGT_ERRIDR_EL1,
.type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
@@ -6819,6 +6826,7 @@ static const ARMCPRegInfo sme_reginfo[] = {
{ .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5,
.access = PL0_RW, .accessfn = access_tpidr2,
+ .fgt = FGT_NTPIDR2_EL0,
.fieldoffset = offsetof(CPUARMState, cp15.tpidr2_el0) },
{ .name = "SVCR", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 2,
@@ -6856,6 +6864,7 @@ static const ARMCPRegInfo sme_reginfo[] = {
{ .name = "SMPRI_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 4,
.access = PL1_RW, .accessfn = access_esm,
+ .fgt = FGT_NSMPRI_EL1,
.type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "SMPRIMAP_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 5,
@@ -8884,6 +8893,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
{ .name = "VBAR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .writefn = vbar_write,
+ .fgt = FGT_VBAR_EL1,
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
offsetof(CPUARMState, cp15.vbar_ns) },
.resetvalue = 0 },
--
2.34.1
- [PULL 04/33] hw/char/pl011: add post_load hook for backwards-compatibility, (continued)
- [PULL 04/33] hw/char/pl011: add post_load hook for backwards-compatibility, Peter Maydell, 2023/02/03
- [PULL 06/33] hw/char/pl011: better handling of FIFO flags on LCR reset, Peter Maydell, 2023/02/03
- [PULL 17/33] target/arm: Disable HSTR_EL2 traps if EL2 is not enabled, Peter Maydell, 2023/02/03
- [PULL 19/33] target/arm: Implement FGT trapping infrastructure, Peter Maydell, 2023/02/03
- [PULL 11/33] target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly, Peter Maydell, 2023/02/03
- [PULL 26/33] target/arm: Mark up sysregs for HFGITR bits 0..11, Peter Maydell, 2023/02/03
- [PULL 21/33] target/arm: Mark up sysregs for HFGRTR bits 12..23, Peter Maydell, 2023/02/03
- [PULL 22/33] target/arm: Mark up sysregs for HFGRTR bits 24..35, Peter Maydell, 2023/02/03
- [PULL 29/33] target/arm: Mark up sysregs for HFGITR bits 48..63, Peter Maydell, 2023/02/03
- [PULL 09/33] hw/arm/virt: Make accels in GIC finalize logic explicit, Peter Maydell, 2023/02/03
- [PULL 23/33] target/arm: Mark up sysregs for HFGRTR bits 36..63,
Peter Maydell <=
- [PULL 25/33] target/arm: Mark up sysregs for HDFGRTR bits 12..63, Peter Maydell, 2023/02/03
- [PULL 30/33] target/arm: Implement the HFGITR_EL2.ERET trap, Peter Maydell, 2023/02/03
- [PULL 16/33] target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1, Peter Maydell, 2023/02/03
- [PULL 15/33] target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps, Peter Maydell, 2023/02/03
- [PULL 13/33] target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3}, Peter Maydell, 2023/02/03
- [PULL 12/33] target/arm: Correct syndrome for ATS12NSO* at Secure EL1, Peter Maydell, 2023/02/03
- [PULL 20/33] target/arm: Mark up sysregs for HFGRTR bits 0..11, Peter Maydell, 2023/02/03
- [PULL 18/33] target/arm: Define the FEAT_FGT registers, Peter Maydell, 2023/02/03
- [PULL 27/33] target/arm: Mark up sysregs for HFGITR bits 12..17, Peter Maydell, 2023/02/03
- [PULL 24/33] target/arm: Mark up sysregs for HDFGRTR bits 0..11, Peter Maydell, 2023/02/03