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[PULL 12/33] target/arm: Correct syndrome for ATS12NSO* at Secure EL1
From: |
Peter Maydell |
Subject: |
[PULL 12/33] target/arm: Correct syndrome for ATS12NSO* at Secure EL1 |
Date: |
Fri, 3 Feb 2023 14:29:06 +0000 |
The AArch32 ATS12NSO* address translation operations are supposed to
trap to either EL2 or EL3 if they're executed at Secure EL1 (which
can only happen if EL3 is AArch64). We implement this, but we got
the syndrome value wrong: like other traps to EL2 or EL3 on an
AArch32 cpreg access, they should report the 0x3 syndrome, not the
0x0 'uncategorized' syndrome. This is clear in the access pseudocode
for these instructions.
Fix the syndrome value for these operations by correcting the
returned value from the ats_access() function.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-3-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-3-peter.maydell@linaro.org
---
target/arm/helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ccb7d1e1712..6f6772d8e04 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3284,9 +3284,9 @@ static CPAccessResult ats_access(CPUARMState *env, const
ARMCPRegInfo *ri,
if (arm_current_el(env) == 1) {
if (arm_is_secure_below_el3(env)) {
if (env->cp15.scr_el3 & SCR_EEL2) {
- return CP_ACCESS_TRAP_UNCATEGORIZED_EL2;
+ return CP_ACCESS_TRAP_EL2;
}
- return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
+ return CP_ACCESS_TRAP_EL3;
}
return CP_ACCESS_TRAP_UNCATEGORIZED;
}
--
2.34.1
- [PULL 21/33] target/arm: Mark up sysregs for HFGRTR bits 12..23, (continued)
- [PULL 21/33] target/arm: Mark up sysregs for HFGRTR bits 12..23, Peter Maydell, 2023/02/03
- [PULL 22/33] target/arm: Mark up sysregs for HFGRTR bits 24..35, Peter Maydell, 2023/02/03
- [PULL 29/33] target/arm: Mark up sysregs for HFGITR bits 48..63, Peter Maydell, 2023/02/03
- [PULL 09/33] hw/arm/virt: Make accels in GIC finalize logic explicit, Peter Maydell, 2023/02/03
- [PULL 23/33] target/arm: Mark up sysregs for HFGRTR bits 36..63, Peter Maydell, 2023/02/03
- [PULL 25/33] target/arm: Mark up sysregs for HDFGRTR bits 12..63, Peter Maydell, 2023/02/03
- [PULL 30/33] target/arm: Implement the HFGITR_EL2.ERET trap, Peter Maydell, 2023/02/03
- [PULL 16/33] target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1, Peter Maydell, 2023/02/03
- [PULL 15/33] target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps, Peter Maydell, 2023/02/03
- [PULL 13/33] target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3}, Peter Maydell, 2023/02/03
- [PULL 12/33] target/arm: Correct syndrome for ATS12NSO* at Secure EL1,
Peter Maydell <=
- [PULL 20/33] target/arm: Mark up sysregs for HFGRTR bits 0..11, Peter Maydell, 2023/02/03
- [PULL 18/33] target/arm: Define the FEAT_FGT registers, Peter Maydell, 2023/02/03
- [PULL 27/33] target/arm: Mark up sysregs for HFGITR bits 12..17, Peter Maydell, 2023/02/03
- [PULL 24/33] target/arm: Mark up sysregs for HDFGRTR bits 0..11, Peter Maydell, 2023/02/03
- [PULL 31/33] target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps, Peter Maydell, 2023/02/03
- [PULL 32/33] target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps, Peter Maydell, 2023/02/03
- [PULL 10/33] sbsa-ref: remove cortex-a76 from list of supported cpus, Peter Maydell, 2023/02/03
- [PULL 08/33] hw/arm/virt: Consolidate GIC finalize logic, Peter Maydell, 2023/02/03
- [PULL 14/33] target/arm: Move do_coproc_insn() syndrome calculation earlier, Peter Maydell, 2023/02/03
- [PULL 28/33] target/arm: Mark up sysregs for HFGITR bits 18..47, Peter Maydell, 2023/02/03