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[PULL 06/33] hw/char/pl011: better handling of FIFO flags on LCR reset
From: |
Peter Maydell |
Subject: |
[PULL 06/33] hw/char/pl011: better handling of FIFO flags on LCR reset |
Date: |
Fri, 3 Feb 2023 14:29:00 +0000 |
From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Current FIFO handling code does not reset RXFE/RXFF flags when guest
resets FIFO by writing to UARTLCR register, although internal FIFO state
is reset to 0 read count. Actual guest-visible flag update will happen
only on next data read or write attempt. As a result of that any guest
that expects RXFE flag to be set (and RXFF to be cleared) after resetting
FIFO will never see that happen.
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230123162304.26254-5-eiakovlev@linux.microsoft.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/char/pl011.c | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index ca7537d8ed2..c15cb7af20b 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -92,6 +92,16 @@ static inline unsigned pl011_get_fifo_depth(PL011State *s)
return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1;
}
+static inline void pl011_reset_fifo(PL011State *s)
+{
+ s->read_count = 0;
+ s->read_pos = 0;
+
+ /* Reset FIFO flags */
+ s->flags &= ~(PL011_FLAG_RXFF | PL011_FLAG_TXFF);
+ s->flags |= PL011_FLAG_RXFE | PL011_FLAG_TXFE;
+}
+
static uint64_t pl011_read(void *opaque, hwaddr offset,
unsigned size)
{
@@ -239,8 +249,7 @@ static void pl011_write(void *opaque, hwaddr offset,
case 11: /* UARTLCR_H */
/* Reset the FIFO state on FIFO enable or disable */
if ((s->lcr ^ value) & 0x10) {
- s->read_count = 0;
- s->read_pos = 0;
+ pl011_reset_fifo(s);
}
if ((s->lcr ^ value) & 0x1) {
int break_enable = value & 0x1;
@@ -450,12 +459,11 @@ static void pl011_reset(DeviceState *dev)
s->ilpr = 0;
s->ibrd = 0;
s->fbrd = 0;
- s->read_pos = 0;
- s->read_count = 0;
s->read_trigger = 1;
s->ifl = 0x12;
s->cr = 0x300;
- s->flags = 0x90;
+ s->flags = 0;
+ pl011_reset_fifo(s);
}
static void pl011_class_init(ObjectClass *oc, void *data)
--
2.34.1
- [PULL 00/33] target-arm queue, Peter Maydell, 2023/02/03
- [PULL 05/33] hw/char/pl011: implement a reset method, Peter Maydell, 2023/02/03
- [PULL 01/33] hw/arm: Use TYPE_ARM_SMMUV3, Peter Maydell, 2023/02/03
- [PULL 02/33] target/arm: Fix physical address resolution for Stage2, Peter Maydell, 2023/02/03
- [PULL 07/33] hvf: arm: Add support for GICv3, Peter Maydell, 2023/02/03
- [PULL 03/33] hw/char/pl011: refactor FIFO depth handling code, Peter Maydell, 2023/02/03
- [PULL 04/33] hw/char/pl011: add post_load hook for backwards-compatibility, Peter Maydell, 2023/02/03
- [PULL 06/33] hw/char/pl011: better handling of FIFO flags on LCR reset,
Peter Maydell <=
- [PULL 17/33] target/arm: Disable HSTR_EL2 traps if EL2 is not enabled, Peter Maydell, 2023/02/03
- [PULL 19/33] target/arm: Implement FGT trapping infrastructure, Peter Maydell, 2023/02/03
- [PULL 11/33] target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly, Peter Maydell, 2023/02/03
- [PULL 26/33] target/arm: Mark up sysregs for HFGITR bits 0..11, Peter Maydell, 2023/02/03
- [PULL 21/33] target/arm: Mark up sysregs for HFGRTR bits 12..23, Peter Maydell, 2023/02/03
- [PULL 22/33] target/arm: Mark up sysregs for HFGRTR bits 24..35, Peter Maydell, 2023/02/03
- [PULL 29/33] target/arm: Mark up sysregs for HFGITR bits 48..63, Peter Maydell, 2023/02/03
- [PULL 09/33] hw/arm/virt: Make accels in GIC finalize logic explicit, Peter Maydell, 2023/02/03
- [PULL 23/33] target/arm: Mark up sysregs for HFGRTR bits 36..63, Peter Maydell, 2023/02/03
- [PULL 25/33] target/arm: Mark up sysregs for HDFGRTR bits 12..63, Peter Maydell, 2023/02/03