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[PATCH 16/18] i386: Fix NumSharingCache for CPUID[0x8000001D].EAX[bits 2
From: |
Zhao Liu |
Subject: |
[PATCH 16/18] i386: Fix NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] |
Date: |
Thu, 2 Feb 2023 17:49:27 +0800 |
From: Zhao Liu <zhao1.liu@intel.com>
>From AMD's APM, NumSharingCache (CPUID[0x8000001D].EAX[bits 25:14])
means [1]:
The number of logical processors sharing this cache is the value of
this field incremented by 1. To determine which logical processors are
sharing a cache, determine a Share Id for each processor as follows:
ShareId = LocalApicId >> log2(NumSharingCache+1)
Logical processors with the same ShareId then share a cache. If
NumSharingCache+1 is not a power of two, round it up to the next power
of two.
>From the description above, the caculation of this feild should be same
as CPUID[4].EAX[bits 25:14] for intel cpus. So also use the offsets of
APIC ID to caculate this field.
Note: I don't have the hardware available, hope someone can help me to
confirm whether this calculation is correct, thanks!
[1]: APM, vol.3, appendix.E.4.15 Function 8000_001Dh--Cache Topology
Information
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
target/i386/cpu.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 96ef96860604..d691c02e3c06 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -355,7 +355,7 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx)
{
- uint32_t l3_threads;
+ uint32_t sharing_apic_ids;
assert(cache->size == cache->line_size * cache->associativity *
cache->partitions * cache->sets);
@@ -364,13 +364,11 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo
*cache,
/* L3 is shared among multiple cores */
if (cache->level == 3) {
- l3_threads = topo_info->modules_per_die *
- topo_info->cores_per_module *
- topo_info->threads_per_core;
- *eax |= (l3_threads - 1) << 14;
+ sharing_apic_ids = 1 << apicid_die_offset(topo_info);
} else {
- *eax |= ((topo_info->threads_per_core - 1) << 14);
+ sharing_apic_ids = 1 << apicid_core_offset(topo_info);
}
+ *eax |= (sharing_apic_ids - 1) << 14;
assert(cache->line_size > 0);
assert(cache->partitions > 0);
--
2.34.1
- [PATCH 05/18] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid(), (continued)
- [PATCH 05/18] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid(), Zhao Liu, 2023/02/02
- [PATCH 06/18] i386: Introduce module-level cpu topology to CPUX86State, Zhao Liu, 2023/02/02
- [PATCH 07/18] i386: Support modules_per_die in X86CPUTopoInfo, Zhao Liu, 2023/02/02
- [PATCH 09/18] i386: Fix comment style in topology.h, Zhao Liu, 2023/02/02
- [PATCH 10/18] i386: Update APIC ID parsing rule to support module level, Zhao Liu, 2023/02/02
- [PATCH 08/18] i386: Support module_id in X86CPUTopoIDs, Zhao Liu, 2023/02/02
- [PATCH 11/18] i386/cpu: Introduce cluster-id to X86CPU, Zhao Liu, 2023/02/02
- [PATCH 12/18] tests: Add test case of APIC ID for module level parsing, Zhao Liu, 2023/02/02
- [PATCH 13/18] hw/i386/pc: Support smp.clusters for x86 PC machine, Zhao Liu, 2023/02/02
- [PATCH 15/18] i386: Use CPUCacheInfo.share_level to encode CPUID[4].EAX[bits 25:14], Zhao Liu, 2023/02/02
- [PATCH 16/18] i386: Fix NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14],
Zhao Liu <=
- [PATCH 14/18] i386: Add cache topology info in CPUCacheInfo, Zhao Liu, 2023/02/02
- [PATCH 17/18] i386: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14], Zhao Liu, 2023/02/02
- [PATCH 18/18] i386: Add new property to control L2 cache topo in CPUID.04H, Zhao Liu, 2023/02/02