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[PATCH 12/18] tests: Add test case of APIC ID for module level parsing
From: |
Zhao Liu |
Subject: |
[PATCH 12/18] tests: Add test case of APIC ID for module level parsing |
Date: |
Thu, 2 Feb 2023 17:49:23 +0800 |
From: Zhuocheng Ding <zhuocheng.ding@intel.com>
After i386 supports module level, it's time to add the test for module
level's parsing.
Signed-off-by: Zhuocheng Ding <zhuocheng.ding@intel.com>
Co-developed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
tests/unit/test-x86-apicid.c | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/tests/unit/test-x86-apicid.c b/tests/unit/test-x86-apicid.c
index f21b8a5d95c2..55b731ccae55 100644
--- a/tests/unit/test-x86-apicid.c
+++ b/tests/unit/test-x86-apicid.c
@@ -37,6 +37,7 @@ static void test_topo_bits(void)
topo_info = (X86CPUTopoInfo) {1, 1, 1, 1};
g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 0);
g_assert_cmpuint(apicid_core_width(&topo_info), ==, 0);
+ g_assert_cmpuint(apicid_module_width(&topo_info), ==, 0);
g_assert_cmpuint(apicid_die_width(&topo_info), ==, 0);
topo_info = (X86CPUTopoInfo) {1, 1, 1, 1};
@@ -74,13 +75,22 @@ static void test_topo_bits(void)
topo_info = (X86CPUTopoInfo) {1, 1, 33, 2};
g_assert_cmpuint(apicid_core_width(&topo_info), ==, 6);
- topo_info = (X86CPUTopoInfo) {1, 1, 30, 2};
+ topo_info = (X86CPUTopoInfo) {1, 6, 30, 2};
+ g_assert_cmpuint(apicid_module_width(&topo_info), ==, 3);
+ topo_info = (X86CPUTopoInfo) {1, 7, 30, 2};
+ g_assert_cmpuint(apicid_module_width(&topo_info), ==, 3);
+ topo_info = (X86CPUTopoInfo) {1, 8, 30, 2};
+ g_assert_cmpuint(apicid_module_width(&topo_info), ==, 3);
+ topo_info = (X86CPUTopoInfo) {1, 9, 30, 2};
+ g_assert_cmpuint(apicid_module_width(&topo_info), ==, 4);
+
+ topo_info = (X86CPUTopoInfo) {1, 6, 30, 2};
g_assert_cmpuint(apicid_die_width(&topo_info), ==, 0);
- topo_info = (X86CPUTopoInfo) {2, 1, 30, 2};
+ topo_info = (X86CPUTopoInfo) {2, 6, 30, 2};
g_assert_cmpuint(apicid_die_width(&topo_info), ==, 1);
- topo_info = (X86CPUTopoInfo) {3, 1, 30, 2};
+ topo_info = (X86CPUTopoInfo) {3, 6, 30, 2};
g_assert_cmpuint(apicid_die_width(&topo_info), ==, 2);
- topo_info = (X86CPUTopoInfo) {4, 1, 30, 2};
+ topo_info = (X86CPUTopoInfo) {4, 6, 30, 2};
g_assert_cmpuint(apicid_die_width(&topo_info), ==, 2);
/* build a weird topology and see if IDs are calculated correctly
@@ -91,6 +101,7 @@ static void test_topo_bits(void)
topo_info = (X86CPUTopoInfo) {1, 1, 6, 3};
g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 2);
g_assert_cmpuint(apicid_core_offset(&topo_info), ==, 2);
+ g_assert_cmpuint(apicid_module_offset(&topo_info), ==, 5);
g_assert_cmpuint(apicid_die_offset(&topo_info), ==, 5);
g_assert_cmpuint(apicid_pkg_offset(&topo_info), ==, 5);
--
2.34.1
- [PATCH 03/18] softmmu: Fix CPUSTATE.nr_cores' calculation, (continued)
- [PATCH 03/18] softmmu: Fix CPUSTATE.nr_cores' calculation, Zhao Liu, 2023/02/02
- [PATCH 02/18] tests: Rename test-x86-cpuid.c to test-x86-apicid.c, Zhao Liu, 2023/02/02
- [PATCH 04/18] i386/cpu: Fix number of addressable IDs in CPUID.04H, Zhao Liu, 2023/02/02
- [PATCH 05/18] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid(), Zhao Liu, 2023/02/02
- [PATCH 06/18] i386: Introduce module-level cpu topology to CPUX86State, Zhao Liu, 2023/02/02
- [PATCH 07/18] i386: Support modules_per_die in X86CPUTopoInfo, Zhao Liu, 2023/02/02
- [PATCH 09/18] i386: Fix comment style in topology.h, Zhao Liu, 2023/02/02
- [PATCH 10/18] i386: Update APIC ID parsing rule to support module level, Zhao Liu, 2023/02/02
- [PATCH 08/18] i386: Support module_id in X86CPUTopoIDs, Zhao Liu, 2023/02/02
- [PATCH 11/18] i386/cpu: Introduce cluster-id to X86CPU, Zhao Liu, 2023/02/02
- [PATCH 12/18] tests: Add test case of APIC ID for module level parsing,
Zhao Liu <=
- [PATCH 13/18] hw/i386/pc: Support smp.clusters for x86 PC machine, Zhao Liu, 2023/02/02
- [PATCH 15/18] i386: Use CPUCacheInfo.share_level to encode CPUID[4].EAX[bits 25:14], Zhao Liu, 2023/02/02
- [PATCH 16/18] i386: Fix NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14], Zhao Liu, 2023/02/02
- [PATCH 14/18] i386: Add cache topology info in CPUCacheInfo, Zhao Liu, 2023/02/02
- [PATCH 17/18] i386: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14], Zhao Liu, 2023/02/02
- [PATCH 18/18] i386: Add new property to control L2 cache topo in CPUID.04H, Zhao Liu, 2023/02/02