Re: [PATCH v5 19/20] hw/isa: derive CPUState from MemTxAttrs in apm_ioport_writeb

[Philippe Mathieu-Daudé]

On 11/11/22 19:25, Alex Bennée wrote:
> Some of the callbacks need a CPUState so extend the interface so we
> can pass that down rather than relying on current_cpu hacks.
>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> ---
>   include/hw/isa/apm.h |  2 +-
>   hw/acpi/ich9.c       |  1 -
>   hw/acpi/piix4.c      |  2 +-
>   hw/isa/apm.c         | 21 +++++++++++++++++----
>   hw/isa/lpc_ich9.c    |  5 ++---
>   5 files changed, 21 insertions(+), 10 deletions(-)


> -static void apm_ioport_writeb(void *opaque, hwaddr addr, uint64_t val,
> -                              unsigned size)
> +static MemTxResult apm_ioport_writeb(void *opaque, hwaddr addr, uint64_t val,
> +                                     unsigned size, MemTxAttrs attrs)
>   {
>       APMState *apm = opaque;
> +    CPUState *cs;
> +
> +    if (attrs.requester_type != MTRT_CPU) {
> +        qemu_log_mask(LOG_UNIMP | LOG_GUEST_ERROR,
> +                      "%s: saw non-CPU transaction", __func__);
> +        return MEMTX_ACCESS_ERROR;

Are you sure it is illegal?

> +    }
> +    cs = qemu_get_cpu(attrs.requester_id);
> +
>       addr &= 1;
>   
>       trace_apm_io_write(addr, val);
> @@ -41,11 +52,13 @@ static void apm_ioport_writeb(void *opaque, hwaddr addr, 
> uint64_t val,
>           apm->apmc = val;
>   
>           if (apm->callback) {
> -            (apm->callback)(val, apm->arg);
> +            (apm->callback)(cs, val, apm->arg);
>           }
>       } else {
>           apm->apms = val;
>       }
> +
> +    return MEMTX_OK;
>   }